ARM unveils next generation 'Thumb-aware' ICs

Electronic News, Oct 27, 1997 by Gale Morrison

San Jose, Calif.--Cambridge, England-based microprocessor core vendor Advanced RISC Machines (ARM) came to the recent Microprocessor Forum here with the ARM9, a new 32-bit RISC processor architecture. The first two products resulting from ARM9 will be the ARM9TDMI and the ARM940T, and ARM says these will represent the company's next generation of "Thumb-aware" processors.

Thumb refers to ARM's 16/32-bit code compression technology offered with the cores. The ARM9 architecture is available for licensing now and pricing is established by the ARM partner licensees based on the customer's specific system-level design requirements.

Symbios Logic, the wholly-owned subsidiary of Hyundai Electronics America, was quick to endorse the new architecture. Tom Lagatta, Symbios VP of marketing and business development, said Symbios will be integrating the ARM9TDMI processor into its core library. The company anticipates using the ARM9 for several future products, including high performance I/O, mass storage, storage management, imaging and other peripheral applications.

Last week, Symbios also added the current-generation--and widely popular--ARM7TDMI 32-bit microprocessor core into its SYM9 0.35-micron process library. When purchased from the library of Fort Collins, Colo.-based Symbios, the core will be known as the SYM7TDMI and will include, among other features, a DSP enhanced multiplier.

Ray Slusarczyk, director of marketing for VLSI Technology's Embedded Processor Group, said his company also will implement the core in its ASIC and ASSP products.

The ARM9 family discussed here in San Jose extends ARM's processor roadmap, and is targeted for several segments, including cell phones, pagers, smart phones and set-top boxes. The ARM9TDMI is the base processor core, while the ARM940T adds features claimed to increase system performance and utility. The ARM9TDMI is said to offer more than twice the performance of an ARM7TDMI processor core, which is currently licensed by a variety of companies including Lucent Technologies (EN, April 21).

Robin Saxby, ARM president and CEO, said the ARM9 offers OEMs standardizing of a core technology a choice in terms of speed, power consumption and die size. "The introduction of ARM9 fortifies our performance roadmap between the ARM7, ARM8 and StrongARM," Mr. Saxby said.

ARM9 features a five-stage pipeline bus, Harvard buses, Thumb extension and full debug access to all programmers' model states. The Thumb code compression extension delivers 32-bit RISC performance at 16-bit system costs through the use of a second, compressed set of 16-bit instructions, which reduces memory use by a third.

The higher end ARM940T adds separate instruction and data caches to the two memory data buses for reduced access time to both instructions and data. The ARM940T also contains a write buffer and a new protection unit meant for embedded operations. A future ARM9 product will extend the protection unit in the ARM940T, ARM revealed, to include a full memory management unit (MMU) so that it might be implemented as a stand-alone microprocessor.

The new ARM9 architecture is also compliant with the Advanced Microcontroller Bus Architecture because it uses the AMBA standard on-chip ASIC bus. Additionally, ARM provides a library of macrocell peripherals which conform to the AMBA standard and are designed "to ease ASIC development."

Projected die size for the ARM9TDMI is 4mm-squared, based on 0.35-micron design rules and 3-layer metal. Estimated die size for the ARM940T is 15 millimeters square, based on 0.35-micron design rules and 3-layer metal. Predicted clock frequency for both devices is approximately 150MHz, with a MIPS rate of 165 at 150MHz. Power consumption for the ARM9TDMI is 1.5mW of power per MHz at 2.5V; consumption for the ARM940T is 4.5mW of power per MHz at 3V.

A future ARM9 product will extend the protection unit in the ARM940T to include a full memory management unit (MMU) so that it might be implemented as a stand-alone microprocessor.