Cadence scores $100M deal for IP services

Electronic News, Nov 3, 1997 by Dylan McGrath

San Jose, Calif.--Cadence Design Systems landed the largest contract in the company's history last week, a $100 million services contract with an unnamed multi-national electronics company. The announcement came just two days after Cadence and Toshiba described the first microprocessor core conforming to intellectual property (IP) reuse standards set forth by the Virtual Socket Interface Alliance (VSI). Cadence said it could not disclose the name of the $100 million customer until later in this quarter.

The agreement appears to be similar to the agreement Cadence has with Toshiba that led to the VSI standards conforming microprocessor, the TX19. Cadence will provide "system to silicon" design services, methodologies, processes, tools and training to leverage and extend the customer's capability to design silicon devices. As with all design services customers, Cadence will be charged with helping the new customer develop best-in-class IP, a process for making that IP available to its customers and a procedure for allowing that IP to be reused within the company.

"We will be helping them set up policies and procedures for the reuse of IP and also help them facilitate that process," said Jim Douglas, Cadence VP of professional services marketing.

The new services deal is worth significantly more than Cadence's previous largest contract, a $75 million agreement to provide design services to Unisys signed in 1995 (EN, March 6, 1995).

Industry Buzz

According to Jennifer Smith, a research analyst with San Francisco-based BancAmerica Robertson Stephens & Co., reports of a large consulting deal looming on Cadence's horizon had been circulating well before last week's announcement. "With Joe Costello leaving, I think there was some concern about the deal actually closing," she said. "It's great to see that it did and that Jack Harding was able to get it done."

Ms. Smith, who suspects the customer is one of the world's largest semiconductor manufacturers, said the contract is significant not only in terms of the amount of revenue, but also because it validates Cadence's new business model. "It's very significant to the business model transition that they are making," she said. "We are beginning to see a shift, with a larger percentage of Cadence's business being consulting."

The joint announcement with Toshiba was also seen as significant by industry insiders. Engineering teams from Toshiba and Cadence collaboratively designed Toshiba's TX19, 32-bit, RISC microprocessor core to be fully compliant with other VSI-compliant "virtual components." Mr. Douglas called this accomplishment the best example to date of Cadence helping a larger, multi-level company to design reusable IP and develop procedures for that reuse. "This is a great example of a situation where we were able to remove a lot of redundancy to come up with a process for IP reuse," Mr. Douglas said. "Right now, we are working with many customers on design reuse principles."

Sees Trend Toward VSI Standards

According to Doug Fairbairn, president of the VSI Alliance, the Cadence/Toshiba announcement is significant, but not unique. He pointed to products announced earlier this year by Fujitsu and Toshiba which also subscribe to VSI standards. He said he sees this announcement as the continuation of a trend toward adopting VSI standards. The announcement is significant in the context that two major companies have chosen to put some focused resources on moving their methodology to be consistent with VSI principals," he said. "That's really the test of the organization, whether or not the companies will adopt the codes and exchange standards that VSI has set forth."

Cadence and Toshiba made another joint announcement last week, announcing the availability of the first advanced design planning methodology based on Cadence's Logic Design Planner (DP). The flow is based on a timing-driven methodology, which merges the domains of logical and physical design to reduce the number of design iterations otherwise required for complex chip design. Toshiba will release its enhanced methodology support based on Cadence's Logic DP for its 0.25-micron dRAMASTIC, embedded array and standard cell system level ASIC families.

"Access to world-class silicon and design methodologies allows Toshiba's customers to meet their extreme time-to-market pressures," said Larry Jordan, senior VP and GM of Toshiba's System IC division.

In yet another announcement last week, Philips Semiconductors and Cadence announced the continuation of a multi-year agreement.