New ColdFire architecture emerges

Electronic News, Nov 3, 1997 by Jim DeTar

Austin, Texas--Motorola this week will unveil version three of its ColdFire 32-bit RISC microprocessor architecture, which the company positions as the successor to it popular but aging 68000 family microprocessors. Although Motorola says it sold 65 million 68000 MPUs into the embedded market last year, it wants to move the market to ColdFire which it views as its primary embedded RISC market platform for the 21st Century.

Sticking to its earlier-released ColdFire core roadmap, the company will unveil ColdFire V3 which will include an enhanced pipeline and feature 8 kilobytes of unified cache memory. Susan T. Cozart, manager of product marketing and applications for Motorola's Imaging and Storage Division, said, "The whole idea was to minimize product memory costs."

To do this, the company optimized its variable length RISC instruction set for code density such that the code ostensibly requires substantially less memory than fixed length RISC chips. ColdFire V3 will be manufactured on a smaller die, 2- to 3mm squared at 0.35-micron process and can operate at up to 100MHz operating frequency with 70 MIPS performance. It can be viewed as another stepping stone toward the company's stated goal to achieve 300 MIPS performance by the year 2001 with ColdFire.

The first V3-based standard products are expected to emerge in 1H98, priced under $20 per unit for an integrated version. Motorola also revealed that the V3 will be quickly followed by V4 in 2H98, while the company at the same time extends its existing V2 product line (the 52xx family) downward toward more cost-competitive price points. 1998 price target for the ColdFire V2 processors is $5- to $7 each.

Ms. Cozart said Motorola is on track with its roadmap and that she made only one adjustment during the last year. "At the first of last year I moved the V2ax (speed increase version) out." Next on the ColdFire roadmap is V4a, due in 1998 with Super Scalar 1 architecture, to be succeeded by V4x in 1999 (speed increase), V5 in late 1999 with Super Scalar 2 V5ax in the year 2000 and the V6a with Super Pipeline architecture and performance rated at 300 MIPS in the year 2001.

Joseph C. Circello, a member of Motorola's technical staff and one of the designers of ColdFire, said, "We have added a couple of stages to the instruction prefetch." The new four-stage instruction fetch pipeline includes instruction address generation, instruction fetch (two cycles) and instruction early decode. "By V3 we needed to go back and balance the pipeline stages," Mr. Circello noted.

The problem with V2 was that it had two basic limitations. First, it used a single-cycle KBus as the processor's local high-speed bus and, second, it was limited by the instruction decode within the decode or fetch stage of the operand execution pipeline (OEP). V3 has addressed these two limitations.

First, the new version has converted to a two-stage pipelined KBus (KC1 and KC2 stages that allows a larger pipe without performance degradation). "By the time most instructions get loaded into the operand they appear as single-cycle instructions," Mr. Circello said.

In addition, Motorola has added what it terms the "IED," or instruction early decode, pipeline stage to the instruction fetch pipeline (IFP). This relocated time-critical decode from the OEP into the IFP.

Motorola also discussed its customer list for ColdFire. Of 19 ColdFire core deployments, 12 of those were internally to Motorola. The other five included companies such as Mitsubishi and Hewlett-Packard. There are presently 10 separate Motorola and external process technologies used on 19 different cores in more than 300 different applications yielding, the company said, more than $400 million in expected revenues over the next three years.