ASIC vendors fight 'productivity gap.'

Electronic News, Nov 17, 1997 by Peter Brown

Mountain View, Calif.--Application specific integrated circuit (ASIC) companies are taking individual approaches to what is increasingly viewed as a growing productivity problem caused by the explosion in the past few years of capacity to multi-million gate levels while tool capabilities have lagged behind.

As reported earlier, in a bid to stem the tide, late last month LSI Logic introduced what it calls the FlexStream design system claimed to speed up system-on-a-chip designs by more than 75 percent for multi-million gate ASICs, and aimed at solving the company's admitted growing design productivity gap (EN, Oct. 27). However, a variety of other ASIC vendors, among them NEC, Lucent Technologies, VLSI Technology and Fujitsu Microelectronics, have all recognized the handwriting on the wall and are attempting to take corrective measures similar to LSI Logic's FlexStream system.

Jordan Selburn, analyst at San Jose-based market research firm Dataquest, said there aren't many people today who want to put millions of gates on a chip, but for those who do the design methodologies are few and far between.

"Definitely there is a gap between what the silicon can do and what is possible to do with today's design methodology," said Mr. Selburn. "I think that FlexStream in particular is a good step in a direction to a comprehensive design methodology in the future."

VLSI's 'Advanced Design Processes'

According to Bob Payne, VLSI Technology's VP of strategic technology, VLSI is working on what he calls "advanced design processes" including creating a host set of tools to be used for intellectual property (IP) delivery and reuse as well as compilers, functional system blocks, flexible system block templates and whatever else designers want on-chip.

"One of the areas we are focusing heavily on is getting these blocks to conform in such a way that they plug-and-play together. Clearly the challenges of deep submicron designs are getting greater with greater libraries," said Mr. Payne. "We will soon be releasing three-million gates per centimeter of core area, so the age of million-gate silicon is here with a vengeance."

VLSI is doing designs based on standard bus architectures so that these IP blocks will be able to "play" together. The company is creating reference designs so a user can develop the operating system and define what subset of capabilities they need to complete the design more efficiently. Mr. Payne said VLSI is also moving away from traditional design flows and evolving its process to give customers early access to hardware so the design is co-developed by VLSI and its customers.

One of LSI Logic's big pushes is the use of alternative technology through small EDA vendors such as Ambit, Sente, Frequency Technology, IKOS and Tera Systems. Although the majority of ASIC vendors have not adopted this strategy, many see a potential to use these small vendors in the future, VLSI being one.

"It turns out we have been talking with some of the same people that LSI has been working with--Ambit and so forth," said Mr. Payne. "Along with seeing new capabilities come from this portion of the EDA marketplace, we believe a lot of the solution is the adoption of an alternative design style which we are implementing."

NEC Electronics' approach to solving its problem is forming partnerships with the big EDA vendors such as Cadence, Mentor Graphics and Synopsys. The motivation here lies in what tools NEC customers want to use in their design flows; NEC wants to support the tools its customers use, said Christina Smith, senior manager of ASIC strategic marketing for NEC.

"Any time you bring in a proprietary solution for tools it unsettles customers and reduces the flexibility customers have with the tools they want to use," said Ms. Smith. "Because an ASIC vendor can't support a particular tool, that can really damage design time. These same partnerships can also solve this productivity problem by letting us work closely with the big EDA companies."

Lucent Technologies is tackling the problem on three fronts: developing proprietary tools, being an active member of the Silicon Integration Initiative (SI2) ASIC Council--which also means being involved in the Virtual Socket Interface Alliance (VSIA)--and working with EDA companies directly--some small, some large--to help them develop appropriate solutions.

Lucent is working closely with Avant! and Synopsys to address the synthesis problem that is a big concern with numerous ASIC vendors, developing its own delay modeling and interconnect modeling technology to answer what it sees as a lack of appropriate technology in the industry.

Possible In-House Development

Fujitsu Microelectronics has also taken up the banner of the large EDA suppliers. However, Bami Bastani, executive VP of the System LSI group for Fujitsu, said in a recent interview with Electronic News that the company is not excluding the possibility of having to do in-house development.

NEC also has taken this approach and works with IP providers to provide a large pool of IP to plug directly into an ASIC design, eliminating some of the routine design work.