Getting ready for deep submicron design

Electronic News, Jan 5, 1998 by Ann Steffora

San Jose--If 1997 was the year for electronic design automation (EDA) vendors to talk about what technology was needed to bring system level integration tools to market, then 1998 is the year when the tree will bear fruit.

Looking forward to 1998, top EDA vendors are optimistic about solving issues for deep submicron (DSM) design. Companies are preparing to either team up to solve the issues laid out over the past year or bring out solutions alone. "1998 will be a pivotal year for the EDA industry. We either have to provide the next generation tools for DSM design, or the semiconductor companies will develop their own tools, becoming the driving force behind tool development," says Gary Smith, principal analyst for worldwide EDA at market researcher Dataquest.

Market leader Cadence Design Systems is taking the "more is better" approach when it comes to solving industry issues. With the announcement of a joint venture with the Scottish government (EN, Dec. 15, 1997), Cadence's Project Alba will "get as many people thinking about design as possible," says Cadence president and CEO Jack Harding.

In 1998, Dataquest predicts the market for tools will reach $2.96 billion, up 23% from 1997, while tool service and maintenance will grow 19% from 1997 to $2.0 billion in 1998.

From a global industry perspective, the impending move to higher complexity designs is taking place now, explains Keith Lobo, president and CEO of Quickturn Design Systems.

"From 1997 to 1999, the most fundamental issue is the significant jump in average complexity," he says. Currently, semiconductor and systems companies design with average complexities of 250,000 to 300,000 gates, however in the next two years, gate complexities will triple, Mr. Lobo says.

50-60 percent of all designs for 1997 was at or above 0.5-micron, Mr. Lobo continues. For 1998 and 1999 he expects that percentage will drop to 12-15 percent, with 70 percent of designs at 0.25-micron by 1999. As a result, the industry can expect to see significant shifts in the landscape, and new tools are needed to address the smaller geometries.

Issues To Be Faced

Key technology issues facing the industry in 1998 include: reuse of soft and hard cores, analysis tools for power, noise and electromigration; DSM design planning tools; resistance-capacitance extraction tools for million gate chip designs; physical verification of complex chips (such as 1Gb DRAM, 300-million transistor FPGA , 100-million transistor microprocessor); system level macro libraries and cores; validation and test suites; and formal verification tools.

In a survey conducted by Dataquest, some of the most desired internally produced tools include those for EMI analysis, power analysis, and internally produced SPICE and signal integrity.

"There is an absolute need for analysis tools right now due to the move to smaller geometries because most of the tools being used now were developed for printed circuit board design which don't always meet a designer's requirements," Mr. Smith commented.

Reuse of the building block in design is also on the minds of many. According to Aart de Geus, president and CEO of Synopsys Inc., "By preserving style, we can enable reuse of IP, and increasingly, this is what customers want." Everyone agrees this is part of the solution to decreasing time to market, and Mr. de Geus admits the way to do it is still in the planning stages. Last June at the Design Automation Conference, Synopsys and Mentor Graphics formed a Design Reuse Partnership that was to yield a jointly authored Reuse Methodology Manual. Mr. de Geus says the manual will be available during the first part of this year.

In an effort to address these key technology issues, EDA vendors are teaming with each other and industry partners to provide solutions for various aspects of the IP evaluation and design process. Aptix, Mentor Graphics and GateField, recently formed the IP QuickUse Initiative to combine products from each to deliver a rapid prototyping system pre-configured for IP evaluation and system on a chip development, called the IP QuickUse Kit.

Along those lines, industry observers note it is likely that Quickturn and Ambit Design Systems will make an announcement early this year in reaction to the IP QuickUse Kit. However, the QuickUse initiative may be slightly favored, sources say, due to the strong IP protection from GateField array, and because Aptix's emulator is more user-friendly than Quickturn's.

Innovative start-ups are also beginning to address some of the technology issues with newer approaches. Mr. Smith says he has never seen better quality startups than in the past four months. Some of these are coming from former Compass employees (such as Virtual Silicon) after Avant! purchased it, along with others that will likely be announced early this year.

Another key technology issue that many EDA vendors are working on is design planning. The DSM design challenge requires that many of the next-generation tools interact from a common data source, which is essential between floorplanning, place and route, RC-parasitic extraction and physical verification tools. Because the amount of electrical, logical and physical data become larger for more complex chips, it becomes difficult to create coherent design flows when there are multiple translations between tools.