Intel to roll out Merced gradually

Electronic News, Feb 23, 1998 by Jim DeTar

San Jose, Calif.--Intel will gradually release its upcoming Merced processor, built on the Explicitly Parallel Instruction Computing (EPIC) technology co-developed with Hewlett-Packard, over the next 18 months. Intel last week at its Developer Forum here provided the most detailed look at the Merced architecture to date, including details on two key features: predication and speculation.

In an interview with Electronic News, Intel principal engineer and computer architect Carole Dulong, and Intel IA-64 director of marketing Ronald E. Curry, provided additional technical specifications for the Merced processor, due out in 1999, and the marketing strategy for the planned MPU line.

Since Intel Chairman Andrew S. Grove told the Forum that Intel has gone from zero to 650 engineers working on the basic PC chips, the question arose how many of those engineers have been pulled off the Merced effort, and whether the attempt by Intel to shift to a more balanced MPU portfolio has delayed the company's planned Merced rollout.

The timetable for introduction of the Merced has not changed, according to Mr. Curry, and Intel has continued to ramp the engineering staff for that project at the same time that it has inaugurated the basic PC chip development team.

"We will continue to disclose portions of the architecture over the next one and a half-years and our target date for introduction is still late 1999," Mr. Curry said. Intel is working on a proprietary chipset for the Merced even as other IA-64 partner companies develop their own chipsets for the planned processor.

"We have not disclosed details of that chipset yet but we are building it from the ground up. Around the middle of this year we will talk about that chipset."

Meanwhile, Ms. Dulong revealed principles of the technology inside Merced including the concept of predication. Traditional architectures use four basic blocks, for example "if," "then," "else," and sum blocks whereas the IA-64 architecture uses one basic block.

"The problem with traditional architectures is the branch. Branch mispredict is a big limiter today. There is mispredict 5 to 10 percent of the time today, accompanied with a large performance loss," she said. "By removing branching, and thereby removing the possibility of mispredicts, an IA-64 processor enhances parallelism, reduces stalls and thereby increases performance.

"In IA-64, two predictions are not on at the same time--they run in parallel. This way, we are able to get rid of the branch," thereby increasing performance over traditional architecture.

A second technique, speculation, is designed to minimize the effect of memory latency. In a traditional architecture, the problem is that increasingly powerful processors are getting faster than the data throughput. Intel will break the data load into two operations: exception detection and exception delivery.