'Bus hold' circuit holds isolation promise for 1394 spec

Electronic News, March 2, 1998 by Sandhya Seshadri, Burke Henehan

Texas Instruments

With the recent advent of multimedia, real-time video and other I/O-hungry applications, the need for high-speed connectivity between a PC and peripheral devices, as well as across-a-system backplane, has become exceedingly urgent. Many of the characteristics of the IEEE 1394 Firewire specification for a high-performance serial bus have made 1394 a very effective solution to this problem.

The 1394 spec defines a high-speed serial bus that can be used on a backplane, such as VMEbus or Futurebus , or as a point-to-point cable-oriented virtual bus for I/O. This article will discuss 1394's use as an I/O bus.

1394 is a transaction-based packet technology. The 1394 serial bus is organized as if it was memory space interconnected between devices. Memory-based addressing, rather than channel addressing, views resources as registers or memory that can be accessed with processor-to-memory transactions.

The 1394 standard mandates a maximum of 16 cable hops. By using 1394 interface devices with three or more ports, a full 1394 network can be achieved with 63 separate nodes or devices on a tree topology. In a 1394 network, each node acts as a repeater to simulate a single logical bus. The limit of 63 nodes to a particular bus segment is a function of the 1394 address space definition. Some 1394 interface devices, which are known as physical layer devices or PHYs, support only one or two ports. A one-port PHY is known as a leaf device because it will be situated at the end of a branch on the network.

The typical hardware topology of a 1394 I/O network consists of the PHY and a link layer. The 1394 specification also defines two software layers, a transaction layer and a serial bus management layer, parts of which may be implemented in hardware. The PHY layer has physical signaling circuits and logic that is responsible for power-up initialization, arbitration, bus-reset sensing and data signaling. The link layer is responsible for formatting data into packets for transmission over the 1394 bus, and it may support both the asynchronous and isochronous communications modes. The speed of the PHY interface device used in a design will determine the serial data transfer rate over the 1394 cable. Currently, PHY devices support speeds of 100-, 200-and 400M.

Many of the 1394 link layer devices available use a store-and-forward scheme of data transfer, meaning the entire packet must be buffered into a FIFO memory before it may be moved out of the FIFO. This is required primarily because these devices do not have built-in thresholding direct memory access (DMA) engines. If the link layer device uses store and forward technology, it must have a FIFO large enough to accommodate the maximum packet size to be used on the 1394 network and the latency involved before a packet can be put onto the 1394 bus.

If a link layer device supports thresholded DMA, a packet can begin transferring from FIFO memory before the FIFO contains the entire packet. A third method of dealing with this is to allow external buffering of data. This must be done along with a mechanism to move that data to or from the 1394 bus only when the bus is ready to receive the data or has data to be received by the node. This data mover (DM) capability is a compromise between the extremes of true DMA and very large FIFOs.

An important compatibility issue involves the PHY and link layer interface. The definition of this interface is not a requirement of the most recent version of the 1394 specification, IEEE 1394-1995. However, it is critical that the PHY and link layer devices are able to communicate. An IEEE committee known as 1394.A is currently updating the 1394 specification to standardize the PHY-link interface. Until this specification is released, system designers must verify that PHY and link layer devices are compatible.

This includes verifying several items, such as compatible setup and hold times across the PHY-link interface. Status transfers from a PHY to a link device are sometimes interrupted. If this occurs, some PHYs retransmit the entire status, while others just transmit the bits that had not yet been transferred. Some PHY implementations do not have the system clock available when the PHY reset pin is asserted while other devices do. In addition, various methods have been used to communicate other functionality between link and PHY devices, including transfers of the link power status (LPS) signal, the configuration manager contender (CMC) signal and the link on (LKON) signal.

Because of the distances between nodes on a 1394 network, different nodes may be plugged into electrical outlets, which could be in different ground domains. If these grounds are connected together by the 1394 cable ground or shielding, a ground loop may exist and current will flow in the cable. These ground loop currents may have several negative effects on the 1394 network, including degradation of data signals on the cable, excessive EMI from the cable, ground currents high enough to damage components in the system and, if the potential difference is large enough, a personal shock hazard.