ASIC Market Surges Upward

Electronic News, July 27, 1998 by Peter Brown

San Jose -- With all of the hype about a slowdown in the PC industry, it is possible to get the impression that most segments of the semiconductor industry are hurting. However, this is not necessarily the case. ASICs, in particular, are making a strong bid for another good year in terms of revenues and profit growth.

Even with gate arrays declining in popularity faster than initially thought in the ASIC market, the transition to standard cells and embedded arrays at most major ASIC houses has been smooth and they have continued to increase revenues at a steady pace.

"ASICs are actually moving ahead of the game in the electronics market because they are too expensive to play in the PC game or in the low-cost cellular phone business," said Jerry Worchel, senior analyst at Cahners' In-Stat Group, a research firm based in Scottsdale, Ariz.

"We are seeing ASICs integrated into things like high-end workstations, networks, servers and other expensive machines. That is why they are doing well."

Even with the decline of gate arrays, competition in the ASIC space has not diminished and in fact may be heating up with advances in deep submicron manufacturing process technology and the proliferation of intellectual property (IP) cores. Because of increased competition, some companies are finding it hard to differentiate and time-to-market and price are becoming the only standards to separate companies.

A TimeCell Matter

This situation is shifting however. Texas Instruments (TI) will today introduce what it claims is a new class of ASICs that combines both standard cells with actual gate array regions on a single chip.

What TI is calling its TimeCell Unified ASIC architecture embeds gate array regions onto a standard cell, much like a hard IP core is embedded onto an ASIC. TI is hoping the technology will launch the company into new areas of the market and move people away from gate arrays and embedded arrays and toward its TimeCell technology.

"80 percent of an ASIC design is usually done with mature re-used logic such as IP cores and other logic that is proven," said David R. Shepard, director of worldwide strategy and business development for ASICs at TI.

"The remaining 20 percent is usually new logic and new ideas where changes are highly likely. With the gate array regions in the ASIC, a designer can put this new logic in and make changes much more quickly than if he was to do it in standard cell logic. Thus, it speeds up cycle times and increases time-to-market."

Mr. Shepard said TI is officially out of the gate array business with the introduction of TimeCell and is only going to invest R&D resources in future versions of standard cells and TimeCell ASICs. The TimeCell devices are manufactured on a 0.18-micron (0.13-L effective) process with production slated to begin in 2H99. TI said by that time it plans to introduce 0.13-micron drawn TimeCell ASICs as well. TI did not reveal prices for the TimeCell technology.

"This is an interesting technology and it does open up some new doors for new applications for TI," said In-Stat's Mr. Worchel. "It is more of an evolutionary step for cell-based technology. Instead of embedding functions in an array TI is embedding the array in a cell-based ASIC, which is a different way to look at things."

SOC It To 'Em

A lot of talk has been uttered about system-on-a-chip (SOC) development in the ASIC space. With the advent of deep submicron process technology, easier access and knowledge of IP cores, and a market starting to demand integration, SOC designs may get a boost. TI is counting on as it rolls out its TimeCell technology, as is Samsung Semiconductor which recently introduced its latest embedded DRAM ASIC touting up to 128 megabits of DRAM and 8.2 million gates on a 0.25-micron ASIC.

This time around, Samsung is targeting its 0.25-micron ASICs specifically at markets that need a high level of integration such as the notebook graphics market, as well as the GPS (global positioning systems) and cellular handset segments.

"In addition to embedded DRAM on board you have complex I/O cores, ARM cores, DSP cores and other communications and networking cores that will be demanded by the system-on-a-chip designer," said Farzad Zarrinfar, associate director of business development for ASIC marketing at Samsung.

"We first started with hard disk drives and networking applications when we first introduced the DRAM ASICs but now we are moving into more applications that will expand our markets in this area and increase our profits."

Mr. Zarrinfar said Samsung is on track to triple its revenue this year in the ASIC division and the Korean company plans to move to 0.18-micron technology sometime next year. The 0.25-micron devices are slated to start sampling in 1Q99 with volume production expected shortly after that. Samsung said non-recurring engineering (NRE) fees start at $200,000.

Bye Bye Gate Arrays

According to Dataquest, the gate array market is forecast to decline from 44 percent of the ASIC market in 1996 to a mere 13 percent of the market by 2002. Evidence to back this up comes from the numerous companies that are dropping out of the ASIC market entirely, including Motorola last year, and LSI Logic earlier this year. Although companies such as AMI and Orbit are picking up portions of the gate array business, most ASIC vendors are migrating their customers to standard cells or embedded arrays.