Cadence Design Systems - a new multi-tool timing-driven design flow - Company Business and Marketing - Brief Article

Electronic News, July 27, 1998 by Chad Fasca, Ann Steffora

Cadence Design Systems will announce today a new, multi-tool timing-driven design flow that addresses some of the technical obstacles preventing the adoption of timing-driven physical implementation methodologies for deep-submicron (DSM) designs. This approach combines a new method of constraint passing with advanced timing-driven design planning, placement, routing, and physical optimization algorithms.

The Cadence System-Level Constraint Timing-Driven Design Flow, is delivering greatly improved chip performance, the company reports: typically 20 percent faster clocks and as much as 6X improvement in design turnaround times, with smaller memory and disk-space requirements. Early trials at NEC have resulted in complex DSM designs being completed four times faster with 20 percent faster clocks, the companies said. This means that potentially, companies can accelerate the sign-off-to-silicon cycle for their customers and getting products to market faster. Motorola is also working to qualify the flow.