Mentor Tool Highlights Timing Verification Need

Electronic News, Sept 7, 1998 by Ann Steffora

Mentor Graphics Corp. recently received qualified production support for its SST Velocity STA tool from Hitachi, Mitel and Oki, further acknowledgement from ASIC vendors that timing is a key issue going forward.

Mentor claims its tool streamlines the iterative analysis process from hours to minutes, and was designed using advanced, proprietary algorithms in a node-based architecture.

A Timing First?

Mentor claims SST Velocity is the "industry's only STA tool offering the power of incremental analysis," and some companies have balked at this statement. Ambit Design Systems, for instance, argues that the static timing analysis engine integrated into BuildGates has always offered incremental timing updates. This is one reason why it has the capacity and speed to rapidly time designs larger than one-million gates. Also, in July, Ambit received commitment from LSI Logic, IBM, Lucent, VLSI and Texas Instruments -- five of the top six ASIC suppliers in terms of both revenue and volume -- to do static timing signoff based on the results of BuildGates integrated static timing engine.

Also announced recently from Mentor is a multi-year, multimillion-dollar deal with Siemens Semiconductors for the licensing of Mentor Graphics' Virtual Library of soft core macrocells to support Siemens' Core-Based Design (CBD) Methodology and the Semicustom Highway Design Environment. Mentor Graphics, through its Inventra IP Division, will also serve as preferred supplier of reusable cores for Siemens.

Improve Time To Profit

Siemens said this relationship will help the company achieve its goal of improving time to profit and growth by adding the necessary IP to its portfolio while enabling them to focus on key IP, providing specific added value to customers. Siemens, with its CBD Methodology and Semicustom Highway, has positioned itself to face the upcoming design challenges.

The company recognizes that a key factor in its success beside quality, price and performance of products, will be its ability to quickly adopt the CBD Methodology before TTM pressure becomes too critical. Siemens' Semicustom Highway Design Environment is a language-based flow used and supported through Siemens' Semiconductors at its semiconductor sites worldwide for custom design of high-performance microcontrollers, telecommunication and consumer ICs and ASICs. The Semicustom Highway flow includes standardized tools for all areas of new product development, from front-end design entry through back-end design verification. Building on the Semicustom Highway, the CBD Methodology delivers and supports a rich set of proprietary and third-party IP for Siemens' internal design teams and partners.

Quick Boost To Functions

Siemens said it chose Mentor Graphics' IP so it could quickly add a large range of standard functions delivered to a consistent standard with a common commercial and legal model, and expects it will help simplify management of its third-party IP portfolio as well. As Siemens transitions into a more design reuse-centric design style, it will use Mentor Graphics as its preferred supplier of IP, and will be assisted by Mentor in bringing its own IP to the open market.

Mentor's Virtual Library contains fixed and parameterized functions including microcontrollers, microprocessors, ISDN building blocks, peripheral controllers, DSP functions, QAM/QPSK, FEC codecs and many more.

This announcement builds on Mentor's Graphics' developing relationship with Siemens Semiconductors, that includes Siemens adoption earlier this year regarding its standardizing on Mentor Graphics' Design-For-Test technology and the adoption of Mentor's Renoir design capture tools.