Agilent's Networking And Computing Group Incorporates Verplex Formal Verification Solution In Design Flow - Product Information

EDP Weekly's IT Monitor, June 11, 2001

Agilent Technologies' Networking and Computing ASIC Group has incorporated the Verplex formal verification software into its design flow.

Verplex's Tuxedo Logic Equivalence Checker (LEC) has been deployed into its advanced hierarchical flows to verify high-performance, multi-million-gate chips for next-generation computing and communications markets. Its designers have used Tuxedo LEC on their chip designs for more than two years.

"Verplex has combined leading-edge technology, ease of use, ease of integration and great support," notes Richard Nash, manager for Agilent's High Performance VLSI Design Automation Group. "As a result, Tuxedo LEC has helped us meet our aggressive product cycles and customers' turn-around requirements. It also has enabled Agilent to formally verify large designs that we have implemented using our most advanced design flows which include physical synthesis and timing-optimized design methodologies."

With more than three decades of design and manufacturing experience, Agilent Technologies is a leading application specific integrated circuit (ASIC) supplier in today's marketplace. Agilent offers state-of-the-art hierarchical design methodology and an excellent design-for-test capability that provides unsurpassed test coverage. These strengths, combined with an extensive intellectual property (IP) portfolio, facilitate rapid integration of quality, high-performance ASICs for applications including communications, imaging and computing.

"Verplex offers the complete tool suite that focuses solely on the verification flow," says Nash. "As a result, Tuxedo LEC provides us with verification independent from the electronic design automation software we utilize to create and implement our designs."

Tuxedo LEC combines speed, performance, capacity and ease of use for the rapid and reliable formal verification of full-chip designs. It compares register transfer level (RTL) code to flattened or hierarchical netlists for multi-million gate designs in minutes or hours, instead of days or weeks required by comparable tools.