Xilinx simplifies QDR II SRAM Memory interfacing with new Virtex-II Pro memory tool kit

EDP Weekly's IT Monitor, June 14, 2004

Xilinx Inc. (Nasdaq:XLNX) has announced the immediate availability of the industry's first programmable 200 MHz QDR II SRAM Memory Tool Kit. Leveraging the high-performance Xilinx Virtex-II Pro Platform FPGA, 200 MHz performance can be easily achieved using mid-speed grade devices, providing substantial development time savings while increasing reliability and reducing time-to-market. The Memory Tool Kit provides a comprehensive resource for system designers interfacing to QDR II SRAM devices and is fully hardware characterized with 200 MHz devices from Samsung.

"A broad range of our mutual customers are using Xilinx Virtex-II Pro FPGAs to interface to our memory devices. By providing a pre-engineered and fully hardware verified turn-key solution on mid-speed grade Virtex-II Pro devices, Xilinx is helping customers achieve further cost savings while substantially reducing time-to-market and design risk," said Tom Quinn, senior vice president of Sales and Marketing for Samsung Semiconductor, Inc. "The Xilinx memory tool kit will enable system architects and designers to quickly and easily implement a robust and reliable QDR II SRAM memory interface resulting in competitive end products."

Fully characterized across process, voltage and temperature on a hardware platform, the QDR II Memory Tool Kit includes a reference design using innovative patented design techniques providing high design margins to maximize QDR II SRAM system design performance. The reference design, available in Verilog and free of charge from the Xilinx website, uses a modular approach to provide distinct physical layer and controller blocks, enabling easy migration to other QDR II/DDR II family devices. The modular design supports any device/package combination, and can be implemented in any Virtex-II Pro device, providing additional flexibility for system designers looking to simplify PCB designs.

The free reference design leverages advanced Virtex-II Pro system features such as digital clock managers (DCMs), abundant low skew local clock resources, flexible SelectIO-Ultra I/O technology (supporting HSTL I/Os required for QDR II SRAM memory interfaces), programmable DDR I/O banks, and XCITE digitally controlled impedance--ideally suited for the clock and data synchronization tasks required--to interface to the newest generations of memory technologies.