Firmware system design for a frequency and time interval analyzer - technical

Hewlett-Packard Journal, Feb, 1989 by Terrance K. Nimori, Lisa B. Stambaugh

When the front-panel PRESET key is pressed, the current configuration is automatically copied into register 0, allowing later recovery. Again, a pointer makes the indexing and copying simple. By keeping all of these parameter subsets the same, we achieve consistency easily.

Measurement Configuration

The measurement manager directs measurement acquisition and processing. It initiates a measurement cycle by programming the input amplifiers and the counting hardware to perform the selected measurement. At the completion of the measurement cycle, it extracts the values of the counters, derives a frequency or time interval, and saves the results in measurement arrays. The measurement manager also performs postprocessing, such as statistics and limit testing.

Continuous Count Architecture. The HP 5371A is based on a continuous measurement architecture. The concept is straightforward: sample the value of a binary counter without disrupting the counting process. Until recently, this was difficult to achieve at high input frequencies and sample rates while maintaining useful resolution. In the HP 5371A, custom sequencer and zero-dead-time (ZDT) counter ICs provide this capability (see article, page 35).

In a typical measurement, input events (trigger edges of signals applied to channel A or B) and edges of a 2-ns reference clock are accumulated in ZDT counters. A ZDT counter contains a 16-bit presettable counter and dual 16-bit latches, all of which have 500-MHz bandwidth.

There are three ZDT counting chains, each consisting of two cascaded ZDT counters. Two ZDT chains can be directed to count events simultaneously on both input channels while the third chain counts the reference clock signal. Thus, simultaneous frequency measurements can be performed on two input channels.

Instantaneous values of these counters are latched in high-speed memory as often as every 100 ns without interrupting the counting process. Latch signals are provided by the sequencer IC, which routes the various clock and event signals to the appropriate ZDT counters.

Supporting this system are digital interpolators and the gate timer. Digital interpolation increases the effective resolution of the system by measuring the phase relationship between the reference clock and the start and stop input events. The time difference between the first or last input event and the following clock edge is quantized to 200 ps.

The gate timer generates sampling intervals and arming delays. It is analogous to the gate time control of a conventional counter. For continuous sampling, however, the timer does not necessarily close the measurement gate. Instead, it defines when the current values of the ZDT counters are to be sampled.

Programming the Sequencer. The sequencer multiplexes latch signals to the ZDT counters. It routes selected arming signals to internal gate flip-flops and implements two-stage sequential arming for precise control of the sampling rate. In general, a measurement cycle may be armed automatically, or by an edge of an input channel, or following a time delay or a number of events referenced to an input channel edge.