Firmware system design for a frequency and time interval analyzer - technical

Hewlett-Packard Journal, Feb, 1989 by Terrance K. Nimori, Lisa B. Stambaugh

Eight 7-bit control registers are configured by the microprocessor to perform the selected measurement. These registers control two similar functional blocks consisting of arming and counting circuits. The arming block selects the sources of latch signals for the ZDT counters. The counting block selects the sources to be counted, such as an input channel or the reference clock, by routing these signals to the appropriate ZDT counters.

Most of the programming data is extracted from a table of control information. An element of this table corresponds to a particular combination of measurement function and arming mode. These settings are retrieved from the data base when the instrument configuration is changed or when a measurement cycle is restarted by the user. Control bits that correspond to specific channel qualifiers are appended.

Programming the ZDT Counters. The ZDT counters accumulate input events or reference clock pulses and output instantaneous or latched values to the microprocessor or DMA-configured measurement memory. They can be programmed to generate an interrupt signal when one or more predetermined conditions have been satisfied. Each ZDT counter interfaces to the microprocessor with a 13-bit control register that contains the latch control bits, interrupt mask, and binary divider ratio.

Three latch modes can be programmed. In the normal operating mode, a ZDT counter is configured to accept latch signals from the sequencer. After a latch signal is received, the value of the counter is latched on the next edge of the input signal or reference clock. If synchronization is unnecessary, the microprocessor can set a control bit that causes the current value of the counters to be latched asynchronously. This is referred to as a forced latch. Finally, the latch signal may propagate from another counter chain.

An interrupt mask defines when a ZDT counter should send an interrupt signal to the sequencer or measurement memory. For example, a ZDT counter can be preset to a value and count incoming events until it rolls over from its maximum value to an all-zero state, when it generates an interrupt signal. This condition is referred to as terminal count. It is primarily used as a qualifier in two-stage arming, such as an event holdoff. To hold off a measurement by a number of events, a pair of cascaded ZDT counters is programmed to its maximum value (2.sup.32 - 1) reduced by the number of events. After that number of holdoff events, the next event will cause the ZDT counters to roll over to zero and generate the terminal count signal, indicating to the sequencer that the number of events has been counted.

Precise time delays can also be generated with this technique. By counting a number of reference clock edges with a ZDT counter, a time holdoff between 2 ns and 8 seconds can be generated with 2-ns resolution.

A special case arises when fewer than 65,536 events are specified. Since the higher-order ZDT counter is not needed, it is preset with a value of zero, and the microprocessor sets a control bit to specify a cascaded latch signal. As events are received by the lower-order counter, they will be counted until a rollover occurs.