Digital waveform synthesis IC architecture - as it relates to the HP 8904A Multifunction Synthesizer - technical

Hewlett-Packard Journal, Feb, 1989 by Mark D. Talbot

Digital Waveform Synthesis IC Architecture

THE DIGITAL WAVEFORM SYNTHESIS integrated circuit (DSWIC) is a digital waveform synthesizer on an IC. It incorporates many signal generation and control functions, is cost-effective, and has multiple uses. The design objectives for the DWSIC called for the following features and functions:

* Four concurrently operating channels with independent frequency, waveform, amplitude, and phase settings

* Amplitude modulation, double-sideband suppressed carrier modulation, frequency modulation, phase modulation, and pulse modulation on one of the channels

* Channels that can be selectively summed together

* Random access memory to provide rapid selection of up to 16 different settings of frequency, amplitude, and phase under internal or external control

* Modulation of one channel from another internal channel, from the sum of channels, or from an external input.

The digital waveform synthesis IC generates one, two, or four time-multiplexed channels (A, B, C, and D) of digitally synthesized waveforms. The output of the DWSIC is converted to analog signals by means of digital-to-analog converters (DACs). Fig. 1 shows a block diagram of the DWSIC.

Control Block

The control block is the interface to a microprocessor and external control logic. With a six-bit data bus, one address line, a chip enable line, and a write enable line, the DWSIC appears to be a write-only peripheral to the controlling microprocessor. Phase reset and SYNC lines provide multiple DWSIC synchronization and fast external parameter change capabilities. The instrument clock input, CLKIN, runs at twice the required internal clock rate. The DWSIC outputs two clock signals: MODCLK and CNTOUT. MODCLK allows synchronization of external modulation inputs and data outputs, and CNTOUT is a fractional multiple of CLKIN.

A 24-bit register, PLLDIV, provides the denominator for the fractional multiply that generates the CNTOUT term. CNTOUT is the overflow from a 24-bit accumulator. The value for CNTOUT is determined by the formula: CNTOUT = CLKIN/2 X PLLDIV/2.sup.24.. The CNTOUT term is used in a phase-locked loop to lock the CLKIN term to a reference in the HP 8904A.

The channel cycle rate can be selected as a function of the CLKIN rate. A number loaded into the clock divide register allows a range of CLKIN/2 to CLKIN/2048 to be selected.

Hop RAM

The hop RAM is a 16-word-by-48-bit RAM memory that enables the DWSIC to provide frequency, phase, and/or amplitude hopping for the HP 8904A. Up to 16 settings for frequency, amplitude, and phase can entered into the hop RAM for channel A. By changing the hop RAM address via the external address lines different hop settings can be selected at a very fast rate. Internal control logic handles the enable and disable settings of the three hop parameters. For example, phase and amplitude hopping can be disabled to produce only frequency hopping without having to remove the phase and amplitude settings from the hop RAM. This feature allows the generation of frequency shift keying signals such as those used in modems, pagers, and other tone signaling devices.

Phase Accumulator

The phase accumulator is the heart of the DWSIC (see Fig. 2). There are four phase accumulators, which are each 24 bits wide and provide 0.1-Hz frequency resolution. The channel timing signals are generated by the control block described above. These signals tell the DWSIC which channel is presently active. The DWSIC can be operated in one-channel mode (only channel A active), two-channel mode (channels A and B active), or four-channel mode (channels A to D active).

Under the control of the channel signals, the phase accumulator multiplexer selects the active channel's accumulator output. This is added by the 24-bit adder to the desired frequency value coming from the FM and frequency sources. The sum, which represents the present phase value, is clocked into the sourcing channel's latch and sent to the waveform generator. The clocks for the accumulators are generated by the accumulator clock generator, which is also controlled by the channel timing signals. The phase clear signal forces the contents of all channel phase latches to zero. This permits phase initialization of all four channels.

The zero crossing logic monitors the active channel and outputs two signals: a level indicating the polarity of the present phase value, and a pulse every time it crosses zero. Both of these signals are available at the output of the DWSIC.

Phase Modulation, Amplitude Modulation, and Waveform

Generation

The phase modulation source shown in Fig. 1 provides the phase offset values that are added to the accumulated phase values from the phase accumulator for each active channel (see Fig. 3). For channel A, this source can contain additional modulation data, and by adding this data to the accumulated phase values, the phase of channel A can be modified by a fixed or varying amount. This results in a phase offset and/or phase modulation for channel A only.