Analog output system design for a multifunction synthesizer - as it applies to the HP 8904A - includes related article on the generation of a phase-locked binary reference frequency - technical

Hewlett-Packard Journal, Feb, 1989 by Thomas M. Higgins, Jr.

Analog Output System Design for a Multifunction Synthesizer

THE WAVEFORMS GENERATED in the digital waveform synthesis IC (DWSIC) in the HP 8904A Multifunction Synthesizer exist only as 12-bit binary numbers at the output of the IC. The output system converts these binary numbers into the desired analog signals.

The first step in this conversion process is the digital-to-analog converter (DAC). Each binary number output by the DWSIC represents the instantaneous voltage of the waveform being generated. Each number represents a sample of the waveform, and the number of samples per second is determined by the clock that drives the DWSIC. The DAC takes each binary number and converts it to the voltage corresponding to that particular sample.

The output of the DAC is a stair-step approximation of the analog signal. If we look at a synthesized sine wave in the frequency domain (see Fig. 1a), we see the desired output signal, along with some high-frequency alias signals characteristic of sampled waveforms. The magnitude of each component is determined by the familiar (sin x)/x envelope. If the maximum frequency in the digitized signal is less than the Nyquist rate, or one half of the sample rate, then these alias signals can be filtered off, removing the stair-step shape. In the real world, ideal low-pass filters cannot be realized, so the required sample rate is somewhat higher than the Nyquist rate.

Because of the (sin x)/x envelope, the frequency response of the output signal is not flat. To flatten the response of the analog signal, the (sin x)/x roll-off must be compensated for, either by digital signal processing techniques while the signal is still in numerical form, or by using a filter with some peaking.

Real-world DACs introduce spurious signals not present in an ideal sampled waveform. The accuracy of a DAC's output is not specified until a given settling time has passed. During this settling time there can be glitches, overshoot, and ringing. In general, these transitions are not uniform, but depend on what two values the DAC is switching between. This adds a noise-like component to the output spectrum, as shown in Fig. 1b. Since much of this noise is present in the same band as the signal, it cannot be filtered out. To eliminate this noise, the output of the DAC can be sampled after it has settled, and the transitions are then determined by the sample-and-hold circuitry. A properly designed sample-and-hold circuit can greatly enhance the signal-to-noise ratio of a digitally synthesized signal.

The block diagram in Fig. 2 shows how these signal conditioning functions are performed by the output board in the HP 8904A. The 12-bit data from the DWSIC is first reclocked by the master clock into the input data latches. This provides proper timing between the DAC and the sampler, and removes any timing skew between the twelve data lines. The DAC converts this data to an analog signal, and the sampler samples the DAC output to remove noise caused by uneven DAC output transitions. The sampler output is buffered to drive one of the two anti-aliasing filters and then another amplifier boosts the voltage of the signal up to the desired [plus-or-minus]10 volts. (Sin x)/x compensation removes the roll-off produced by the sampling, and a step attenuator allows control of signal level without sacrificing dynamic range. Finally, the floating output amplifier provides the current drive necessary for a 50-ohm source, and provides a floating output to avoid system ground-loop problems.

Sampler

As described earlier, the function of the sampler is to sample the output of the DAC after it has settled to its specified accuracy and hold this voltage until the next sample. This results in lowering the noise produced by inconsistent transitions in the DAC. The sample-and-hold circuit holds the previously sampled voltage for the first half cycle while the DAC settles, and for the second half cycle it tracks the DAC output. This 50% duty cycle provides maximum settling time for both the DAC and the hold circuitry.

The sampler driver is a limiting amplifier that provides a differential, high-current drive signal to the diode bridge. A transformer at the output of the sampler driver allows the sampling bridge to float and improves the balance of the drive signal. The combination of the differential driver and the transformer produces a very well-balanced, isolated drive signal and prevents high levels of the drive signal from getting onto the sampled signal. If high levels of the drive signal were to get through the sampler, the sampler buffer would be overloaded, causing severe distortion. The small amount of drive signal that does get through the sampler is filtered out at the output of the sampler buffer.

The sampler buffer is the most critical circuit on the output board. It must have an extremely high input impedance so as not to drain the 15-pF hold capacitor, and must have very low distortion for audio signals in the presence of high-level, high-frequency alias signals. Any dc offsets are magnified by ten in the following amplifier stages, so the buffer must have a very low offset. In addition, it must have an extremely flat frequency response and be able to drive the low and nonresistive impedance of the filters that follow it.