EMC design of the HP 54600 Series oscilloscopes: by a combination of electronic circuit design and mechanical shielding techniques, the design meets German FTZ standards and, with optional shielding, most U.S. military standards for electromagnetic compatibility - Technical

Hewlett-Packard Journal, Feb, 1992 by Kenneth D. Wyatt

All ICs are liberally bypassed from the supply pin to ground with 0.01-[micro-F] or 0.1-[micro-F] chip capacitors. Each package has one or more as appropriate. The larger ASICs have both bypass capacitors and filter networks to control noise generation.

The last primary RFI reduction technique used is a simple RC filter network on the microprocessor clock buffer/divider Mg. 5). Clock rise times are a major cause of emissions and are often 2 ns or less, depending upon the logic family used. Very often, these fast edges are unnecessary.

If the Fourier series of a trapezoidal waveform is analyzed, it will be noted that the envelope containing the noise current harmonics starts rolling off at a 20-dB/decade rate and then decreases at a 40-dB/decade rate with a break frequency that depends only on the rise (or fall) time of the square wave Fig. 6). By slowing the edges of the clock signal, the harmonic content can be substantially reduced. Radiated clock harmonics have been reduced by 6 to 12 dB merely by adding this simple RC network.

Related to the edge speed problem is the use of fast devices. In one case, a transistor with an fT of 5 GHz was used to amplify an 80-MHz trigger signal. The rise time for this device was 2 ns and we were measuring a strong harmonic at 800 MHz. By changing to a different device with an [f.sub.T] of 1 GHz and a rise time of 3.5 ns, the harmonic amplitude was reduced by 6 dB.

Printed Circuit Board Design

The circuit board is a six-layer, single-sided, surface mount design. Full ground planes are used to provide both a ground plane and additional isolation between trace layers. All secondary power is isolated with L filters consisting of a multiturn ferrite core and multiple chip capacitors at the board power connector. This prevents circuit board noise currents from traveling out the power supply wiring.

Another suppression technique is component grouping by function and speed. The power input and filtering are located at the rear of the board, well away from other sensitive or noisy connectors. The crystal oscillators are located close to the power filter section and away from sensitive analog inputs. The analog circuitry is located on one side of the board, while the high-speed digital circuitry is located on the other. Plenty of filtering and decoupling is used on all supply traces to prevent noise currents from flowing from noisy areas to sensitive areas of the board. Much of the analog circuitry is contained within a cast shield to prevent interference from external fields.

The circuit board is also attached to the steel deck, which serves three purposes. Besides serving as a structural portion of the system, the deck provides about 10 dB of low-frequency (60 Hz) shielding and also serves as an image plane.3 An image plane acts to confine external fields generated on the circuit board to the area between the board and the plane. The large metal surface forces any electric (E) and magnetic (H) field lines impinging on its surface to rotate orthogonally. As the image plane is moved close to the board, this forced rotation tends to cancel both the E and H fields that originate on the board. This technique (which is free) further reduces the radiated emission sources within the oscilloscope and helps lower system RFI.