Fast turnaround of a structured custom IC design using advanced design tools and methodology

Hewlett-Packard Journal, April, 1997 by Rory L. Fisher, Stephen R. Herbener, John R. Morgan, John R. Pessetto

Through the use of several new tools and methodologies, a small team of engineers was able to design and verify a 1.7-million-FET chip in eight months. The tools and methodologies used included a set of guidelines and timing constraints that were met by the customer, a data path compiler, a highly tuned custom multiplier cell that was used in 87 locations, and an automated top-level power connection scheme.

The HP IMACC chip was developed to provide image processing capabilities. The initial target application is medical imaging with geological applications as a potential area of expansion. The graphical capabilities of IMACC include spatial filtering, edge detection and enhancement, image pan and zoom, image rotation, and window and level control. IMACC consists of three major components:

* The convolver circuit has a 3 x 3 programmable kernel* and can perform low-pass or high-pass spatial filtering, edge enhancement, and other functions.

* The interpolator is an implementation of a 4 x 4 bicubic convolution kernel.(*) The interpolator can be configured to perform pan, zoom, and rotation.

* A RAM-based lookup table is used for windowing and leveling of image pixel intensities.

In support of the various user-selectable operating modes, any or all three of the functional blocks may be active at a time. The order of operations can be changed as desired, with the single limitation that the convolver must precede the interpolator if both modules are in the chain. When the image visualization accelerator board (IMACC is the heart of this board) is attached to the HP HCRX graphics subsystem, simultaneous convolution, zoom, rotation, and window and level control of 1024-by-1024 pixel, 16-bit medical images at 40 frames per second are possible. The accelerator can process more than 40 million pixels per second independent of the number or order of internal operations.

Customer Interaction

As a result of our experience in designing numerous ICs for various customers, our laboratory has developed some practical, informal guidelines for designing ICs. At the beginning of the IMACC project, we met with the customer (another HP laboratory) and discussed these guidelines along with project goals. The guidelines we provided to our customer are as follows:

* The prime directive: Signal groups such as multistate drivers on a single bus, multiple set signals into a flip-flop, or multiple set signals into a multiplexer, may cause drive fights and therefore need to be completely decoded from the current state of the control machine so that one and only one will fire. This requirement must hold even if the chip comes up in a random state. Exceptions to this have caused significant delays in schedule right before tape release.

* Signals require a consistent naming convention.

* Update flip-flops on the falling edge of the clock (single-edge timing).

* When glitchless values are required (Gray code counters, etc.), they must come directly out of flip-flops. Resets are typically heavily loaded and will probably cause timing problems. Have each control block latch its own version of the chip reset, then generate its own local reset. This helps timing at the expense of latency.

* Don't design multistate paths. Complete timing analysis of such a path is not possible in any design tool.

* Don't set and dump the same FIFO or RAM location at the same time.

* Keep Synopsys blocks small.

* Keep large register files in the data path. Use no clock uncertainty (skew) in Synopsys. It will be there, but is better allowed for by reducing the period. Don't allow Synopsys to try to fix hold problems. There should be none by design.

* When setting your timing constraints, allow some slack for RC delays, the local clock generator, and incremental delays that will be introduced when actual routing capacitances are substituted into the timing model. For example, 15 ns might be a good period constraint at 60 MHz.

* As constraints (timing and loading) become more accurate, make sure to continue to update them in your design. Accurate is better than conservative in Synopsys.

* Simulate at the board level as soon as possible.

* Simulate timing between blocks as soon as possible (schematic simulations are fairly accurate).

* Simulate the chip coming up in random states as soon as possible. A proven way to do this is to make sure the chip can come up with unknown values in all memory elements, including flip-flops and registers.

The highest-priority design goal was to have a working IMACC system to demonstrate at an upcoming conference. We created a schedule consistent with this goal incorporating the necessary checkpoints. Two of the most important checkpoints: * We were to deliver a top-level, schematic-based Verilog gate model to the customer so they could begin regression tests at the system level. This allowed them to identify design problems early. * The customer was to freeze the function of major data path blocks by a scheduled date. This allowed us to construct the artwork in a single pass.