New midrange members of the Hewlett-Packard Precision Architecture Computer Family - includes related article on double-sided surface mount process - technical

Hewlett-Packard Journal, June, 1989 by Thomas O. Meyer, Russell C. Brockmann, Jeffrey G. Hargis, John Keller, Floyd E. Moore

The circuitry of the 8M-byte memory board released with the Model 825/Series 925 was designed to allow future expansion to 16M bytes with only minor modifications. Slight modifications were made to allow either 8M or 16M bytes to be loaded at the factory using the same board. The 8M-byte version simply omits the bottom-side DRAMs and bypass capacitors. The NMOS-III VLSI memory controller was designed to support 2M, 4M, 8M, or 16M bytes, including single-bit error correction, double-bit error detection, and support for battery backup of the memory contents in case of main power failure.

Although very little new electrical design was required in the 16M-byte memory board, time was spent in verifying operational parameters and increasing the manufacturability of the board. It was designed with all the test points on the bottom side to be electrically tested in an HP 3065 single-sided probe fixture in manufacturing. This design allows a less expensive and more reliable test fixture and the use of the same fixture for both the 8M-byte and 16M-byte versions.

Since the 16M-byte board was the first design to use HP's new SMT-2 process, the printed circuit board development software was modified to evaluate and verify the design of the board before sending data out for board fabrication. The flexibility of HP EGS allowed easy addition of the necessary features to route circuitry to bottom-side components and varify SMT-2 design rule compliance.

Acknowledgments

The Model 835/Series 935 project benefited by having a highly motivated team of individuals involved in all aspects of design, manufacturing, test, and marketing. Our thanks go to everyone who was involved. Particular thanks go to Denny Georg, R&D lab manager, and Russ Sparks, R&D section manager, for their complete support throughout the project. Thanks also go to Dan Osecky, Glenda McCall, Lisa Quatman, Jerry Schell, and Bob Headrick for their management help.

The authors also wish to recognize the efforts of Ann Kloster, Charlie Shilling, Lynne Christofanelli, Alisa Scherer, and Jim Murphy for hardware design, Paul French, Willy McAllister, Pirooz Emad, Dave Goldberg, Gene Mar, Kevin Morishige, Greg Averill, Annika Bohl, Balbir Pahal, Ram Ramjadi, and Valerie Wilson for FPC design, Mark Hodapp, Rose Maple, Jeff Kehoe, and Ed Ogle for firmware and diagnostics, Mark Stolz, Rick Butler, Jeff Rearick, and Asad Aziz for chip and board test development, and Charlie Kohlhardt and Keving Burkhart for providing 30-MHz VLSI. Thanks also go to Andy Vogen, Conrad Taysom, Keith Walden, and Madi Bowen for their help with SMT design and to Spencer Ure, George Winski, Don Soltis, Arlen Roesner, Gary Stringham, Steve Hanzlik, Marcia Franz, and Karyn Jarvis for handling other manufacturing issues.