Measuring the ECG signal with a mixed analog-digital application-specific IC

Hewlett-Packard Journal, Oct, 1991 by Wolfgang Grossbach

At the outputs of the differential amplifier in each of the three channels, the signal path is split into two parts. For the two main channels, the auxiliary path goes out of the integrated circuit to the pace pulse detector. The pace pulses are identified by their higher-frequency content in the range of 1 to 4 kHz, but only the presence of a pace pulse has to be detected, not the time dependent signal itself. Therefore, it is unnecessary to construct the whole signal path with this large bandwidth. After the pace pulse detector output, low-pass filtering of the ECG signal begins.

For ECG filtering, a minimum lower corner frequency of 0.05 Hz is required. The large capacitor and resistor values needed could not be integrated and therefore the signal is routed from the chip into external filter sections, one for each channel. By means of internal switches, three low-end comer frequencies (0.05 Hz, 0.5 Hz, 3.5 Hz) and two high-end comer frequencies (40 Hz and 130 Hz) can be selected.

The signal flows out of the chip, through the external filters, and back into the chip. It then goes through the main gain stage, which has switchable gain of 40 or 160 depending on the signal amplitude and the resolution needed on the screen. After passing the gain stage, the signal is filtered with a second-order switched capacitor stage to achieve the comer frequency of 130 Hz with as small a tolerance as possible.

The three analog channels described so far are connected to the inputs of a one-of-eight multiplexer, which sequentially scans these three channels and five auxiliary channels every 2 milliseconds. The output feeds into the ADC, a 10-bit converter that has less than /-1 LSB differential nonlinearity and a conversion time of 20 us. An 8-by-10-bit dynamic random access memory holds all the conversion results temporarily until they are transmitted via a parallel-to-serial converter out of the chip to the module microprocessor. In the opposite direction, all control information is transferred into the chip over this serial interface and latched. The use of a serial data conversion scheme made it possible to use only three output lines and a 28-pin package. Fig. 3 is a photograph of the ECG ASIC chip.

Pace Pulse Detection Circuit

The dual pace pulse detector is also an ASIC. Its analog parts are built entirely in switched capacitor technology.

This had the advantage of avoiding laser trimming, minimizing wafer area, and thus reducing cost. This chip generates two logic output signals for each channel, indicating whether a pace pulse with either positive or negative polarity is present in the input signal. The information is polled by the microprocessor and sent to the algorithmic software.

Test Considerations

It was clear from the beginning that testing the ECG chip would be a challenge because of the large number of parameters to be measured. The specifications describing the functionality are split into two parts: internal and external specifications. The internal specifications can be tested with wafer probes and help the vendor optimize the production process. They are consistent with the external specifications, which are measurable from outside the chip and are accessible to the customer. The external specifications are the link between the ASIC design and the printed circuit board design and were used as guidelines throughout the design and verification process. Automated test equipment has been set up at HP to test the ECG chip via its serial interface. The same test equipment is used by both the vendor and HP to reduce the number of false measurements resulting from different measurement setups.