The EISA connector

Hewlett-Packard Journal, Oct, 1991 by Michael B. Raynham, Douglas M. Thom

Providing backward compatibility in the EISA connector hardware for ISA I/O boards resulted in a bilevel connector design that provides pins for both bus standards in the same connector.

One of the reasons for the rapid growth of the personal computer (PC) market is the wide variety of compatible software and hardware peripherals available for these machines. This compatibility has been provided by a defacto industry-standard bus specification called Industry Standard Architecture (ISA). Although started with the original IBM PC system architecture, the standard has evolved to where it can be adopted by any PC manufacturer, thus providing a stable platform for software and hardware development.

The EISA (Extended Industry Standard Architecture) is a superset of the ISA 8-bit and 16-bit architecture. The important features of the EISA specification include:

* Full compatibility with the ISA standard. ISA 8-bit and 16-bit expansion boards can be installed in EISA slots.

* Support for a 32-bit address path and for 16-bit or 32-bit data transfers for CPU, DMA, and bus master devices. (A bus master is a device that drives the address lines and controls the signals for a bus cycle.) An efficient synchronous data transfer protocol that provides for normal single transfers and the cycle control required to execute burst cycles up to 33 Mbytes/s.

* Automatic translation of bus cycles between EISA and ISA masters and slaves.

* Support for a bus master architecture designed for intelligent peripherals. With EISA-based computers the bus controller can operate some of the lines on behalf of the bus master.

* A centralized bus arbitration scheme that supports preemption of an active bus master or DMA device. The EISA arbitration method grants access to the bus for DMA devices, DRAM refresh, bus masters, and bus and CPU functions on a fair, rotational basis.

* Level-triggered, shareable interrupts. Edge-triggered operation ensures compatibility with interrupt-driven ISA devices. Level-triggered operation facilitates sharing of a single system interrupt by a number of devices.

* Automatic configuration of system and expansion boards. EISA expansion board manufacturers provide configuration files and product identification information so that during system initialization these boards can be automatically configured into a system (see page 84). More detailed information about the EISA bus can be found in references 1, 2 and 3.

Engineers from HP's personal computer group were involved in defining the physical and electrical design of the I/O bus, the board connectors, and the logic controlling bus timing for the EISA bus specification. Their most obvious contribution was the "double-decker" EISA connector. This connector has two levels of pins. The first level maintains ISA compatibility and the second level adds the pins for the EISA bus specification. This article will describe the EISA connector and some aspects of the development partnership that led to the development of the connector and I/O card hardware.

Background

The EISA connector was an important part of the implementation of the EISA bus standard. At the time we started this project there was no connector available that met the general electrical and mechanical characteristics required for EISA. Some solutions were proposed but they were discarded because they were not competitive in size and electrical performance. The IBM Microchannel* bus architecture had already doubled the pitch of contacts from 0.100-inch to 0.050-inch centers on their connectors, and it was felt that the EISA solution must use this contact density to be competitive. The technical responsibilities for the proposed EISA bus design were divided among a small group of the original EISA consortium companies. The responsibilities for the definition, development, and sourcing for the EISA connector were given to Hewlett-Packard and Compaq Computer Corp. Because the EISA connector was the first physical evidence of the EISA hardware, it became important from a public relations standpoint that the design not only be backward compatible with ISA, but also be perceived as technically superior (e.g., higher-performance, well designed, etc.). The availability of production connectors was a serious concern because once the design was finalized the potential demand for connector hardware would be very high. To ensure that a high-volume supply would be available, and to manage the technical risks, it was decided to recruit least two major connector manufacturers to develop and produce the connector. HP and Compaq Computer Corp. recruited Burndy Corporation and AMP

* Microchannel is the bus architecture developed for the IBM Personal System/2 computers. Incorporated into the EISA consortium to participate in the design.

Organizational Challenges

The connector project was managed primarily by a joint team of HP and Compaq engineers representing the EISA consortium. The team attracted connector manufacturers using the number of customers within the consortium to convince the manufacturers of the magnitude of the business opportunity for EISA connectors. The preliminary design requirements were established by HP and Compaq Computer Corp. as part of the EISA technical specification. This technical specification, which was revised and published periodically by the consortium, was the single specification that all connector vendors used to develop their specific connector designs. The periodic revision of the specification proved very valuable in maximizing the collective technical contributions of the connector vendors. All potential vendors could obtain a set of technical requirements by joining the EISA consortium. These vendors could also recommend technical ideas for the design, which, if adopted, would become part of the specification. All technical contributions incorporated into the specification became the intellectual property of the consortium, and therefore, became available to all members. This process produced a very robust and thorough connector specification by using the collective efforts of all participants, some of whom were direct competitors. Fig. 1 shows the design and development information flow during this process.