ECL clocks for high-performance RISC workstations - emitter-coupled logic - circuits used to distribute clock signals in HP 9000 Series 700 workstations - Technical

Hewlett-Packard Journal, August, 1992 by Frank J. Lettang

In the HP 9000 Series 700 workstations, clock signals are distributed using differential ELC circuits, and the VLSI chips have CMOS inputs operating at ECL levels. Critical clock delay signals are routed on 50-ohm striplines on printed circuit board inner layers.

In synchronous computers the clock system generates the rhythm that makes everything work, so clock performance plays an important role in determining the maximum operating frequency of a high-performance workstation. Clock design and distribution are important system design issues that separate semifast computers from extremely fast computers.

To make an effective clock system it is important to minimize both clock jitter and skew since both effects reduce the time available for the computer to do useful work between each clock tick. Component variations, electrical noise, temperature, and supply voltage changes all combine to increase the amount of jitter and skew found in a clock system. The clock system design must minimize these problems, not only in the clock circuits themselves but also in the components that use the clocks.

In HP 9000 Series 700 workstations, high-speed clock signals are distributed using ECL logic because of its superior timing characteristics and faster rise and fall times. To improve the performance, nearly all the ECL signals are routed differentially from the outputs of low-skew clock distribution ICs. Using both the signal and its complement to drive the differential inputs of an ECL device greatly reduces the effects of differences between the rise and fall times. CMOS differential inputs operating at ECL thresholds are used on all the high-speed VLSI chips. This minimizes on-chip delay and skew by making the conversion to internal CMOS levels more efficient. While all of this may seem a bit expensive, the performance of the clock system affects the performance of all of the devices that connect to it, and spending a little more money on the clock system saves a lot of money in other areas.

Fig. 1 is a block diagram of the Series 700 clock system. The system starts with an ECL oscillator running at twice the processor frequency. This oscillator drives the clock input of an ECL finite state machine that generates differential ECL clock signals at the processor frequency and half the processor frequency. These signals need a specific phase relationship. The state machine always reverts to the proper transition pattern without the need for a reset signal. From the state machine, differential ECL signals drive clock distribution chips and ECL-to-TTL converters.

The state machine is implemented using a number of ECL high-speed edge-triggered flip-flops. Since all the flip-flops are on the same die, skew and jitter are minimized. The oscillator has a frequency stability of 100 ppm, which contributes only about 2 ps to the clock system jitter. Oscillators with good frequency stability are essential to designing high-performance clock systems. As clock speeds increase beyond that of the current Series 700 workstations, providing good frequency references will become an even more important challenge. For the current clock system the maximum measured combined jitter and skew is about 75 ps and is largely the result of noise and component behavior.

A differential ECL level translation circuit is needed between the clock state machine, which uses ECL referenced to 3 volts, and the clock distribution chip used by the VLSI chips, which is referenced to 0 volts. This eight-resistor network (Fig. 2) properly terminates the complementary ECL signals at the characteristic impedance of the striplines that carry them (50 ohms) while generating the input signal needed by the ECL clock distribution IC. Since the output impedance of this network is relatively high compared to what can be achieved on the printed circuit board, the passive network is located physically as close as possible to the clock distribution chip.

Using an HP 54121T time-domain network analyzer, the response of this circuit to input pulses is easily verified. The response is shown in Fig. 3. The printed circuit board implementation generates an edge delay of about 298 ps and degrades the 700-ps ECL rise time slightly. This is largely the result of the parasitic capacitance and inductance present in any real implementation of a level translation network. It is always useful to verify designs of this type with actual measurements and check for unexpected parasitic effects.

The high-speed system bus uses TTL clocks running at half the processor frequency. These clocks are generated by an ECL-to-TTL converter that doubles as a TTL clock distribution chip. A differential ECL delay line, implemented as a pair of striplines, is placed between the state machine and this converter to optimize setup and hold times on the system bus. ECL signals are ideal for realizing highly accurate signal delays because of their crisp edges and high-quality terminations. No level translation is required on this path since the converter expects 3-volt-referenced ECL and that is what the clock state machine generates.