RF signal generator single-loop frequency synthesis, phase noise reduction, and frequency modulation - features of Hewlett-Packard's Performance Signal Generator family; includes sidebar on delay line discriminators and frequency-locked loops

Hewlett-Packard Journal, Oct, 1989 by Brad E. Andersen, Earl C. Herleikson

RF Signal Generator Single-Loop Frequency Synthesis, Phase Noise Reduction, and Frequency Modulation

THE THREE PERFORMANCE SIGNAL GENERATORS (PSG) share a common synthesis block diagram, as discussed in the article on page 6. This method of synthesis is quite different from many signal generators designed for low noise. For example, the HP 8662A uses seven phase-locked loops (PLLs) and seven voltage-controlled oscillators (VCOs) for frequency synthesis, and the HP 8642A uses six PLLs and 12 VCOs. In contrast, the HP 8644A, 8645A, and 8665A PSGs use one PLL, one VCO, and up to two frequency-locked loops (FLLs). The simplicity of this new design results in lower parts count, higher reliability, and no spurious mixing outputs. The FLLs are added when lower phase noise is desired and each instrument uses the FLLs whenever possible.

In this article, operation of each loop and its effect on noise performance will be discussed. The frequency modulation scheme will also be explained, including loop crossovers and the various operating modes.

Frequency Synthesis

The voltage-controlled oscillator used in the HP 8644A and 8645A covers the 515-to-1030-MHz octave, while the HP 8665A VCO covers the 3-to-6-GHz octave. A PLL locks the VCO to a reference frequency with high accuracy and fine resolution. A pretune DAC is used to tune the VCO over this octave with enough resolution for the PLL to acquire lock easily. Without the PLL, the frequency accuracy is on the order of several hundred kilhertz. This is generally inadequate for most applications. The phase noise without a PLL is just that of the free-running VCO. Fig. Fig. 1 illustrates a free running VCO with pretune circuitry for tuning, and shows an idealized phase-noise plot.

The phase-locked loop is placed around the VCO to lock its frequency to a stable reference frequency as shown in Fig. 2. A fractional-N technique (see box, page 28) is used to achieve a frequency resolution of 0.01 Hz. This particular fractional-N PLL operates from 257.5 to 515 M Hz (each signal generator's VCO output frequency is divided down to meet this requirement) and achieves excellent spurious performance, typically lower than -60 dBc.

An operating characteristic of a PLL is that the phase noise of the loop's RF output will either be that of the reference input or the noise of the PLL circuitry. In this case the noise rolls down with the reference and then with the 1/f characteristic of the fractional-N PLL until it gets to the noise floor of the PLL at -85 to -90 dBc/Hz. The noise then stays at this level throughout the bandwidth of the PLL, even beyond where the raw VCO noise is less than the PLL's. To optimize the noise performance, the PLL bandwidth is chosen to be equal to the frequency at which the raw VCO noise intersects the noise floor of the PLL. This turns out to be about 3 kHz. The resulting phase noise plot follows the reference to the PLL floor, the PLL floor to the PLL bandwidth, and then the VCO noise itself.

Phase Noise Reduction

To reduce the VCO phase noise, one or more frequency-lock loops can be placed around the VCO. A user-selectable FLL based on a 70-ns delay line discriminator is standard in the HP 8644A and 8645A. The design of this discriminator is described in the article on page 34.

Fig. 3 shows a block diagram and a phase noise plot of this circuit arrangement. When this loop is selected, the PLL sees a lower-noise VCO, so the PLL bandwidth is reduced to coincide with the new crossing of the PLL noise floor and the cleaner VCO noise. The new PLL bandwidth is about 350 Hz. The FLL bandwidth determinees the noise floor for offsets below the FLL bandwidth frequency. Extending the bandwidth further to get a lower floor can produce peaking of the phase noise beyond the bandwidth point because of phase and gain margin problems. The FLL bandwidth of about 1 MHz provides an adequate noise floor and avoids peaking of the noise beyond the bandwidth frequency. See page 30 for more information on the use of delay line discriminators for noise reduction.

The noise characteristic of the FLL discriminator can be shown asymptotically by calculating the noise floor and the delay line corner frequency (see fig. 4). The noise goes up with a 20-dB/decade slope for frequencies less than this corner frequency and then up with a 30-dB/decade slope when the 1/f corner of the discriminator (usually the phase detector) is reached. The FLL discriminator noise floor is lower than the VCO's, so the resulting phase noise beyond the FLL bandwidth is that of the VCO.

The overall phase noise graph follows the FLL noise down at 30 dB/decade until the 1/f point, where the slope becomes 20 dB/decade. When the phase noise reaches the VCO noise level at the FLL bandwidth, the slope becomes zero. This becomes the noise pedestal of the FLL-stabilized VCO. The phase noise plot remains flat out to the FLL bandwidth, and then follows the VCO phase noise characteristic for higher frequency offsets from the carrier.