Design considerations in a fast hopping voltage-controlled oscillator - the VCO design in the Hewlett-Packard HP 8645A Agile Signal Generator

Hewlett-Packard Journal, Oct, 1989 by Barton L. McJunkin, David M. Hoover

Design Considerations in a Fast Hopping Voltage-Controlled Oscillator

IN ITS FAST HOPPING MODE of operation, the HP 8645A Agile Signal Generator can switch to a new frequency in less than 15 microseconds with an accuracy of one part per million or better. This article describes the fast hopping VCO block diagram and the five major technical challenges that had to be met to build the fast hopping VCO.

System Architecture

The HP 8645A uses a 515-to-1030-MHz oscillator whose stability is controlled by a fractional-N phase-locked loop (PLL), by a frequency-locked loop (FLL) based on a delay line discriminator, or by both the PLL and the FLL. Fig. 1 is a block diagram of the system.

The frequency-to-voltage conversion characteristic of the discriminator is inverted by placing the discriminator in a feedback path around the VCO. The stabilized VCO now has the voltage-to-frequency characteristics of the inverted discriminator. For fast switching speed, the feedback loop must be wideband and high-gain without degrading the stability of the discriminator.

The ideal model for the FLL loop gain is a single integrator with a unity-gain crossover frequency of 1 MHz. Because of the relatively flat gain and excess phase shift of the discriminator, the gain margin of the loop required more attention than the phase margin.

As explained in the box on page 30, the frequency-to-voltage conversion characteristic of the delay line discriminator is a repetitive function of the form:

[V.sub.out] = [V.sub.peak]Sin(([omega] - [[omega].sub.0])[tau]),

where [V.sub.peak] is the peak voltage from the phase detector, [omega] is the input angular frequency (radians/second), and [tau] is the time delay of the line (seconds). Although each input frequency results in only one output voltage, the inverse is not true. Each output voltage can indicate a multitude of frequencies. The inverted response of the discriminator-stabilized VCO is single-valued only over a small range of ([omega] - [[omega].sub.0])[tau] < [ or -]90 degrees at the FLL phase detector. This means that the VCO must be pretuned to witin 1/4[tau] Hz of the final frequency before the discriminator will stabilize the VCO to the correct frequency. To ensure that no transient condition can result in the FLL's locking the VCO to the wrong frequency, the FLL is designed to have a pulling range less than 1/4[tau] Hz. The pulling range is limited to this value by a diode limiter on the FLL VCO control line.

The standard signal detector operation of the instrument uses the fractional-N loop to phase-lock the VCO to the reference signal and the discriminator to reduce the phase noise of the oscillator.

Learn Sequence

Before the system enters the fast hopping mode, it must learn the correct values for the pretune DAC (digital-to-analog converter), phase shifter, FLL DAC, and PLL DAC. The learn sequence is as follows.

The fractional-N loop phase-locks the VCO to the desired frequency. The tune line offset is used to optimize the pretune value. The phase shifter is used to null the FLL phase detector within [ or -]6 degrees of quadrature. The FLL DAC is used to cancel the phase detector offset at the input of the low-noise amplifier. The PLL DAC is used to replace the PLL tune line with an equivalent dc voltage. This procedure is followed for each frequency that is hopped to. The DAC values are then saved in internal memory to be called back when the instrument hops to that frequency.

In the fast hopping mode, the PLL is opened and the discriminator controls the frequency accuracy of the signal generator in addition to reducing the phase noise of the oscillator. Since the discriminator controls the frequency accuracy of the signal generator, it is necessary to optimize the stability of the discriminator for best performance. The three components of the discriminator that have the greatest effect on frequency stability are the power amplifier, the phase shifter, and the delay line. Besides the discriminator, two other components can cause considerable frequency error: the feedback loop and the VCO pretune circuit.

Power Amplifier

The power amplifier drives the input of the discriminator with a leveled RF signal. Automatic level control (ALC) maintains the power amplifier output at six volts peak into the backmatch resistor. This high power level is necessary for low-noise, high-sensitivity operation.

Absolute accuracy of the power amplifier ALC loop is not as important as switching speed and stability. The ALC loop has a minimum bandwith of 500 kHz and must settle to within 0.012% of the final level within 15 microseconds. This is the kind of stability that is necessary to keep the AM-to-]Phi]M conversion of the phase detector to acceptable levels. Since the AM-to-[Phi]M rejection of the phase detector is only 10 dB worst-case, 0.012% AM can cause 0.1 ppm of frequency error in the FLL.

The extreme stability specification for the AM level requires a very accurate level detector. The detector is a peak-to-peak Schottky diode detector with an output level of -12V dc. Because of the high output level, temperature compensation of the Schottky diodes was not necessary.