Design considerations in a fast hopping voltage-controlled oscillator - the VCO design in the Hewlett-Packard HP 8645A Agile Signal Generator

Hewlett-Packard Journal, Oct, 1989 by Barton L. McJunkin, David M. Hoover

The detector output is compared to a stable reference voltage and the error signal is integrated and applied to the modulator at the input to the power amplifier. The modulator is a limiter amplifier with a variable bias. The modulator has 15 dB of linear range with the output varying from 5 to 20 dBm.

The final ALC loop bandwidth varies from 500 kHz to 2 MHz across the 500-MHz-to-1040-MHz frequency band. Since the bias loop of the limiter is used to control the modulator, and since the power amplifier is near limiting, the bias loops for both the limiter amplifier and the power amplifier are wideband loops. To reduce the overall detector error signal, the power amplifier bias circuit uses an integrator in the bias loop for high dc gain.

Phase Shifter

The main design goal for the phase shifter was to produce no more than 0.2 ppm of error in the stabilized VCO from t = 5 microseconds to t = 10 minutes. This requires phase stability within <0.0012 degree. Other design goals were low loss, good input/output match, low phase noise, good phase stability with temperature, monotonicity of phase shift with frequency, fast switching (<5 [mu]s for <0.0012[degree] stability), and excellent long-term phase stability.

Two specifications drove the choice of implementation: phase noise and switching speed. A varactor phase shifter could not satisfy both conditions. With a switching speed specification of 5 microseconds, sufficient filtering for phase noise was not possible. The topology that was chosen is a transmission line structure with double-pole double-throw pin switches. Five binary-weighted phase shift elements have phase shifts of 90[degrees], 45[degrees], 22.5[degrees], 11.25[degrees], and 5.6[degrees] at 500 MHz. Because of the transmission line design, the minimum phase resolution at 1000 MHz is 11.25[degrees].

The initial switch design used discrete pin diodes and simple driver circuits. A large phase drift occurred when the current was switched from one diode to another. The drift was caused by the heating of the pin diodes, which affected the RF resistance and forward bias voltage. The initial phase drift was approximately 0.5[degree] from t = 5 [mu]s to t = 10 s.

Dual monolithic pin diodes are now used in the DPDT switches. Since one or the other of the diodes is forward biased, the total power dissipation in the diode chip is constant. Also, the driver circuits were replaced with stable current sources. The constant bias improves the long-term stability. These changes reduced the phase drift from t = 5 [mu]s to several minutes to something on the order of 0.02[degree].

The remaining phase drift was difficult to track down. It was finally traced to shifts in the dielectric constant of the printed circuit board material caused by localized heating. The heating was caused by both bias and RF power dissipation. The shifts in dielectric constant caused changes in the group delay of the transmission lines. Placing the design onto a Teflon board allowed the phase shifter to meet its short-term phase stability specification.