Receiver design for a combined RF network and spectrum analyzer - radio frequency; HP 4396A - includes related article on digital signal processing techniques - Technical

Hewlett-Packard Journal, Oct, 1993 by Yoshiyuki Yanagimoto

Spectrum Resolution

Suppose the signal from the ADC has no images (all rejected), no aliases (anti-aliasing effectively applied), and the sampling frequency is [f.sub.s]. An N-point FFT applied to the incoming signal to get its spectrum gives the following resolution bandwidth (RBW):

RBW=k x [f.sub.s]/N (1)

where k is the 3-dB bandwidth factor of the window function. Table I lists some of these bandwidth factors for different window functions.

                             TABLE I
                        3-dB Bandwidth Factors

Windows Functions                          Bandwidth Factor

   Rectangle                                    0.89
   Hamming                                      1.30
   Blackman                                     1.68

If [f.sub.2] is constant and we want to ensure that the required RBW is wide enough, suitable values for k and N must be chosen since the RBW is a function of these two variables. In the HP 4396A, a suitable power of two is selected for N and then a window with a suitable k can be designed.

Necessity of Decimation

If a narrow RBW is required, according to equation 1 a larger N, a lower[f.sub.s], and a smaller k would make it possible. However. a larger N needs more memory and the FFT coherent quantization error would be an important factor. We found through simulation that N = 4096 is the maximum limit to avoid this error in the HP 4396A, and k cannot be less than four to meet the specification of passband ripple for the window functions.

Directly reducing [f.sub.s] in hardware is not feasible for the HP 4396A. Therefore, we digitally convert the sampling rate of a signal from the given [f.sub.2] lower value [f.sub.s]/M, where M is an integer value called the decimation factor[2]. Thus,

RBW = k x ([f.sub.s]/M)/N (2)

Note that once the signal is M-to-1 decimated, the information bandwidth of the result of one FFT is divident by M. Also, in the decimation process the appropriate anti-alias digital filtering should be performed before the M-to-1 sample rate reduction because the sam reduction because the sample rate reduction generates aliasing M times. The executive time of a decimation is based on the filtering process.

Two-Stage Decimation

For the case in whch the whole computation of the resolution bandwidth is done in batch mode using equation 2, the amount of data required to be stored is:

Two-Stage Decimation

For the case in which the whole computation of the resolution bandwidth is done in batch mode using equation 2, the amount of data required to be stored is:

M x N L

where L is the number of taps(*2) of the digital anti-aliasing filter before decimation. This number is too large for hardware implementation.

Decimation processing in real time could reduce the amount of memory to the order of N, but the 56001 cannot the finish the whole M-to-1 decimation calculation in a sampling period (12.5 [mu]s =1/80 kHz). Therefore, we separate the decimation into two stages, that is,

M = M1 x M2. (3)

First, M1-to-1 decimation is performed and then M2-to-1 decimation is performed. On the condition that the necessary anti-aliasing is performed in the second decimation stage, some aliasing can be accepted in the first decimation stage. This means that the necessary amount of anti-alias filtering can be much smaller in the first decimation stage. Therefore, the first decimation is performed in real time since the amount of data required to be stored is reduced to: