Receiver design for a combined RF network and spectrum analyzer - radio frequency; HP 4396A - includes related article on digital signal processing techniques - Technical

Hewlett-Packard Journal, Oct, 1993 by Yoshiyuki Yanagimoto

M2 x N L (4)

where M2 < M. Fig. 1 illustrates the concept of this two-stage decimation process.

In the first decimation stage, the impulse response of the anti-aliasing filter is convolved with the signal, which is sampled with the rate [f.sub.s]. Only ever M1-th sample of the filtered output is saved. Consequently, the sample rate is converted from [f.sub.s] down to [f.sub.1], which is equal to [f.sub.s]/M1. Note that aliasing occurs between [f.sub.e] and [f.sub.1] - [f.sub.e], but the effective information band (0 to [f.sub.p]) is not affected.

In the second decimation stage, anti-alias filtering is performed and only every M2-th sample of the filtered output is saved. Consequently, the sample rate is converted from [f.sub.1] down to [f.sub.2], which is equal to [f.sub.1]/M2 = [f.sub.s]/M1/M2. In this stage, complete anti-aliasing is required so that the range from [f.sub.e] to [f.sub.1] is completely eliminated by the filter.

(*1) Decimation in digital filtering is the process of digitally converting the sample rate of a signal from a given rate [f.sub.s.], where [f.sub.s] [is less than] [f.sub.s].

(*2) Taps refers to the number of coefficients used in the FIR filter.

The passband width (2 x [f.sub.p]) of the filter is the effective information bandwidth of the FFT and the step width of the stepped FFT.(*1) The wider this is, the fewer the FFTs for the same span, but the more difficult it is to realize anti-alias filtering. In the HP 4396A, [f.sub.p] is 75% of [f.sub.2]/2.

According to equations 3 and 4, a larger value of M1 (smaller value for M2) can save more memory. In the HP 4396A, M2 is always two. Table II shows the parameters used in computing the RBW.

                            Table II
                         RBW Parameters
RBW           1      3     10     30     100    300    1k    3k

(Hz)

N           4096    4096   4096   1024   4096   1024   256   128
M1           50      16      5      5
M2            2       2      2      2
[f.sub.2]    80      80     80     80     80    80      80    80

(kHz) [f.sup.2] 0.80 2.5 8 8 (kHz)

EBW 0.60 1.875 6 6 10 10 10 10 (kHz)

N = Number of FFT points

M1, M2 = First and second decimation factors

[f.sub.s] = Sampling frequency

[f.sub.2] = Second demimated sampling frequency ([f.sub.s]/M1/M2)

EBW = FFT effective information bandwidth (75% x f.sub.s]/M1/M2 for decimation, 10 kHz for direct FFT)

This two-stage decimation is performed in the signal processing section section of the HP 4396A, which is described below.

Signal Processing Block Diagram

The signal processing blcok diagram in Fig. 2 shows the three blocks involved in signal processing in the HP 4396A. In the first block (analog process) the incoming signal is filtered and converted to digital format. In the second stage (real-time process) digital mixing and the first decimation are performed in real time. Finally, in the third block (batch process), second decimation, windowing, and FFT are performed. For cases in which the RBW is equal to 100 Hz, 300 Hz, 1 kHz, or 3 kHz no decimation is required, so only windowing and FFT are performed. This direct FFT process is also indicated in Fig. 2.