Expanded memory for the HP Vectra ES personal computer - includes related articles on LIM Expanded Memory Specification 3.2 and 4.0 and on the difference between expanded and extended memories - technical

Hewlett-Packard Journal, Dec, 1988 by Gary W. Lum, Milton J. Lau, Wesley H. Stelter

Expanded Memory for the HP Vectra ES Personal Computer

THE VECTRA ES EXPANDED MEMORY CARD is a memory subsystem consisting of a hardware card and a software driver for the HP Vectra ES Personal Computer. The key design objectives for this subsystem were to:

* Conform to industry standards, including LIM EMS 3.2 and 4.0 (see box, page 61)

* Provide a high-performance expanded memory system to support Microsoft Windows and the NewWave environment

* Provide a high-performance memory system to support extended memory applications (see box, page 62, for an explanation of extended and expanded memory).

The design challenge was to provide superior performance and yet remain compatible. Both LIM EMS 4.0 and 3.2 define a protocol for using expanded memory, but EMS 3.2 includes support of function calls 10 and 11, which dictate a specific memory architecture, and several major applications make use of them. These software functions define not only the memory cards' I/O port addresses, but the I/O data bit assignments as well. The memory card had to conform to these definitions--a high-performance memory system that was not register-compatible with the LIM EMS 3.2 specification would not meet our objectives. How does one contribute within such a strict definition of compatibility?

The project team began by addressing the level of compatibility required by end-users. Clearly, full support of LIM EMS 4.0 was a requirement for Microsoft Windows, and because some major industry applications use LIM EMS 3.2 functions 10 and 11, supporting these was also necessary. Extended memory support was required for support of new operating systems, such as OS/2. None of these applications specifies a particular mechanical configuration of a memory card, or a maximum CPU or memory clock speed. Research showed that customers wanted at least 1M bytes of additional memory and required any upgrades to be user-installable. Industry trends showed that a maximum configuration of 6M to 8M bytes would be competitive in the next generation of memory cards. Therefore, we required full compatibility with LIM EMS 3.2 and 4.0, but had some freedom in the mechanical configuration, memory configuration, and electrical performance of the card.

Given these constraints, the ES expanded memory card definition evolved into a card that provides the following features:

* 100% compatibility with LIM EMS 4.0 and 3.2

* Daughter board configuration that does not take up a standard Vectra I/O slot.

* Up to 8M bytes of expanded or extended memory

* User-installable memory upgrades

* All 8M bytes of memory running at the same memory speed as the Vectra ES motherboard memory

* EMS 4.0-specific hardware for superior expanded memory performance.

Each of these features adds capability to the Vectra ES Computer, yet does not compromise the required compatibility models. A proprietary motherboard/memory-card interface was defined that makes the 8M-byte memory array appear to the 80286 CPU as motherboard memory. Since the new LIM EMS 4.0 function calls do not specify a hardware architecture, proprietary high-performance circuitry was designed to assist these calls. Surface mount logic ICs and the latest DRAM technology allow both the new logic and an 8M-byte memory array to fit on a single card.

Hardware Architecture

The ES expanded memory card is partitioned into three major blocks (Fig. 1): a single 8M-byte DRAM array, extended memory logic, and expanded memory logic. The extended and expanded logic blocks are two independent memory systems. Separate extended and expanded memory addresses are generated each memory cycle, and one is chosen depending on the type of cycle (defined by the state of the highest microprocessor address lines).

The 8M-byte DRAM array is organized as four independent 2M-byte banks (the reason for this is explained later). Each bank is 18 bits wide--16 bits of data and 2 parity bits--which allows a minimum memory configuration of 2M bytes, with upgrades in 2M-byte increments. On-board logic handles all timing and refreshing for the memory array. Each bank can be assigned to either expanded or extended memory via DIP switches, so the user can specify a combination of both kinds of memory.

The extended memory logic is straightforward (Fig. 2). Comparators and DIP switches define a starting address and an ending address on any 1M-byte boundary. These signals generate VALID_EXT_ADRS, which is used in a lookup table to determine which of the four physical memory banks is used. Any memory bank not assigned in the lookup table is considered to be expanded memory, allowing a combination of both extended and expanded memory. DIP switches define all extended memory parameters, since extended memory must be defined at system power-up, before any software driver can configure the card.

The expanded memory logic, shown in Fig. 3, is considerably more complex. Four logically independent banks of eight map tables each, bank-switching logic, and a set of I/O registers make up this block. The I/O registers are used to configure the bank-switching logic and update map table contents. Once the map tables are programmed, they begin managing the expanded memory pages whenever memory addresses are presented to the board.