Baseband vector signal analyzer hardware design - HP 89410A electronic test device - Technical

Hewlett-Packard Journal, Dec, 1993 by Manfred Bartz, Keith A. Bayern, Joseph R. Diederichs, David F. Kelley

The operation of the correlator can be described mathematically. At the output of the ADC, the digital representation of the kth sample of the input signal plus dither can be described as:

[Aout.sub.k] = [D.sub.k](1 e) [S.sub.k],

where [D.sub.k] is the kth dither value, [S.sub.k] is the kth input signal, an d e represents the dither gain error. Following the digital subtraction of the dither, the digital output signal consists of the digitized version of the input signal plus the residual dither errors:

[Dout.sub.k] = [D.sub.k]e [S.sub.k]

The correlator multiplies each output sample by the corresponding dither sample, yielding:

[MATHEMATICAL EXPRESSION OMITTED]

These values are consecutively added to the contents of the digital accumulator, yielding an accumulating average whose expected value is given by:

[MATHEMATICAL EXPRESSION OMITTED]

Because the dither signal is uncorrelated with the input signal, the expected value of their product is zero and the long-term average value of the accumulator is:

[MATHEMATICAL EXPRESSION OMITTED]

Thus the expected value of the correlation samples is proportional to the dither gain error. Summation of these samples in the accumulator acts as a digital integrator. The feedback dither error signal consists of the 8 most-significant bits (MSB) in the accumulator. It is fed to an 8-bit AGC DAC whose analog output modulates the amplitude of the dither signal at the output of the high-speed dither DAC to drive the dither subtraction errors to zero.

Dither Gain Control Loop Analysis

The dither gain control loop is a mixed analog and digital control system. A simplified diagram is shown in Fig. 7a. Lumping the correlator and accumulator gains into a single feedback gain [Beta] and ignoring the s-domain effects of the zero-order hold associated with the AGC DAC and the loop shaping filter results in the simplified z-domain loop shown in Fig. 7b. The transfer function of the dither error derived from the simplified output error signal in the z domain is given by:

[MATHEMATICAL EXPRESSION OMITTED]

For the correlator loop the combined system gain of the dither DAC and ADC, A.sub.o, is approximately 1 and the feedback gain [Beta] is <<1. For [A.sub.o] =

1, the dither error goes to zero. For [A.sub.o] approaching 1, the dither errors

are proportional to [Beta].

The bit size of the accumulator dominates the feedback gain constant [Beta], which determines the time constant of the loop. The effect of the dither gain loop on the input signal is to produce a small amount of amplitude modulation. The magnitude and frequency of the AM sidebands are made negligibly small by choosing the accumulator size to be sufficiently large (36 bits). This corresponds to an approximate [Beta] value of 2(36-12) for a 12-bit sample size, or modulation sidebands that are 144 dB down. In addition, one can estimate the loop bandwidth from the loop equation:

[MATHEMATICAL EXPRESSION OMITTED]

For [Beta] = -144 dB = 10.sup.144/20 the loop bandwidth is 0.5 Hz yielding a time constant of 2 seconds. These estimates are within an order of magnitude.