Baseband vector signal analyzer hardware design - HP 89410A electronic test device - Technical

Hewlett-Packard Journal, Dec, 1993 by Manfred Bartz, Keith A. Bayern, Joseph R. Diederichs, David F. Kelley

Wide Bandwidth in a High-Impedance System

One of the best ways to achieve good linearity an distortion performance over a given bandwidth is to design so that the bandwidth of interest is a relatively small part of the overall bandwidth of the system. Distortion often increases dramatically at frequencies near the bandwidth limit of a circuit. Thus, a low-distortion design may reasonably employ circuits with ten times the intended application bandwidth.

Such is the case with the HP 89410A input. Designed to be used to I0 MHz, some of its constituent blocks have bandwidths on the order of 100 MHz or more. However, with some signal runs on the input board on the order of six inches in length, transmission line effects cannot be ignored.

The normal solution is to use a doubly terminated transmission line design. This design calls for carefully controlled transmission line impedances matched on both the source and receiving ends. However, two factors preclude the use of doubly terminated transmissions lines in this application. One is the 6-dB signal loss at the source-to-line divider, and the other is the inability to source the required current to drive matched 50-ohm or even 100-ohm transmission lines and maintain distortion performance.

Instead, a hybrid structure is used. Long signal runs have a small series back-match resistor at the driving end. Some runs also have capacitively coupled termination resistors at the receiving end. These circuit elements control the peaking in frequency response that would otherwise occur, but do not cause a large signal loss or draw large currents that would adversely affect distortion performance.

Attenuators and Input FET

The first elements in the ranging architecture of the input are a pair of 20-dB attenuators. These are designed for a 1-megohm system (presenting 1 megohm to the preceding circuitry when loaded with 1 megohm).

The attenuators transition from resistivc dividers to capacitive dividers in the tens-of-kilohertz region. Each attenuator requires a tunable-capacitor flatness adjustment. The first attenuator also has an input capacitance adjustment to balance the input capacitance for the attenuated and nonattenuated settings.

Ac coupling is provided by a 0.1-[micro]F capacitor, giving a lowfrequency roll-off at nominally 1.6 Hz. The ac coupled and dc coupled paths are carefully balanced for capacitance to ground. Without this careful balance, a frequency response difference would exist between the two paths at high frequencies, unaccounted for by calibration.

The input FET is the only discrete amplifier stage in the input. A source follower with current-source bias is constructed from a matched pair of JFETs in a single package. IDSS (drain current at zero gate-to-source voltage) matching between the two devices to [ or-] 5% requires an adjustment to the current source to obtain 0Vdc across the stage. Signal gain is nominally about -1 dB for the stage.

The FET device used, a special high-transconductance, high-IDss type, is capable of maintaining distortion performance well in excess of 90 dB at 10 MHz with the -12 dBm signal levels found at this point in the circuit.