Inphi Corp. breaks the speed barrier with 80 Gbps indium phosphide integrated circuits - Business - Brief Article - Statistical Data Included

Fiber Optics Business, Feb 28, 2002

Inphi Corp. announced that it has demonstrated demultiplexers running at a data rate of greater than 80 Gbps. These integrated circuits (ICs) convert a single high-speed serial data stream into four differential outputs within telecommunication transceivers. They are designed in indium phosphide (InP), an extremely fast semiconductor material that is paving the way for robust, error-free OC-768 networks.

Inph's 80 Gbps achievement in indium phosphide exceeds recently published results in silicon germanium (SiGe), which reached half-rate speeds of only 56 Gbps. Moreover, although Inphi's half rate demultiplexer operates at a much higher speed than the SiGe circuits, it dissipates the same amount of power. At a reduced data rate of 40 Gbps, for example, Inphi's half-rate demultiplexer dissipates only 400 milliwatts of power, which is approximately one third the power as SiGe haif-rate circuits operating at the same speed.

The Inphi 80 Gbps circuits are based on a half-rate architecture, which is equivalent in terms of clock rate to a full-rate circuit running at 40 Gbps. These half-rate circuits dissipate 1.3 watts of power at 80 Gbps operation and 400 milliwatts of power at 40 Gbps operation--levels comparable to existing OC-192 components.

In a half-rate design, the clock driver samples the incoming signal on both the rising edge and the falling edge of the clock. By contrast, in a full-rate design, the signal is sampled on only one clock edge, either rising or falling but not both. Most commercial ICs are based on full-rate architectures; half-rate architectures are more sensitive to actual transport system variations such as duty cycle distortion and thus are generally used only in short-reach and lower-performance systems.

In October, Inphi announced full-rate packaged multiplexer and demultiplexer prototypes at speeds greater than 50 Gbps with a power consumption of less than 900 milliwatts. These products are currently sampling to customers. They are based on Inphi's InP/CMOS chipset architecture, which combines the speed and low power of InP components with highly integrated, cost-competitive standards compliant CMOS components. Whether at a half-rate or full-rate clock, the Inphi architecture to date has yielded superior results in terms of both speed and power dissipation compared with SiGe technology.