Chips: Samsung Samples First JEDEC-Compliant DDR SDRAM

Edge: Work-Group Computing Report, August 24, 1998

                   Samsung DDR SDRAM First Samples

Feature             Component                Module

Density:              64Mb         32/36MB, 64/72MB, 128/144MB

Configurations:      x8/x16                 x64/x72

Packaging:     66-Pin TSOP Type II   184-pin Unbuffered DIMM

Clock Rate:                   100/125MHz

Data Rate:        200/250Million bits per second per pin

Peak Bandwidth:    500Million Bytes per second per chip

Power Supply:                    3.3V

I/O Supply Level:            3.3V or 2.5V

I/O Interface Level:            SSTL_2

The continued evolution of traditional multiplexed DRAMs took a key step closer to reality Monday as Samsung Semiconductor, Inc. announced availability of first samples of a fully JEDEC-compliant Double-Data-Rate Synchronous DRAM (DDR SDRAM).

This accomplishment is the latest step in bringing this enhanced SDRAM to the server, workstation and data communications system markets.

Samsung has begun sampling beta customers with a 64Mb DDR SDRAM and will make engineering samples available this quarter. "Hewlett-Packard has actively participated in the development of the industry standard for DDR memory," stated Steve Erasmus, Director of Component Quality and Technology at Hewlett-Packard. "We have started testing Samsung's JEDEC-compliant 64Mb DDR SDRAM and expect this work to result in DDR being ready for our initial applications."

Samsung achieved the world's first working prototypes last fall to verify the feasibility of the signaling interface and protocol. In December 1997, Samsung demonstrated prototype DDR DIMM modules operating at 1.06GB/s (66MHz) in a test system with a DDR-ready chipset from VIA Technology before JEDEC (Joint Electronics Device Engineering Council).

DDR SDRAM component and module standards were established through JEDEC in the first half of 1998. This new pre-production silicon meets the full JEDEC specifications. Samsung's first silicon has been fully tested functionally and parametrically over operating temperature and voltage ranges.

Production versions of the DDR modules will include both unbuffered and registered versions with speeds up to 133MHz (266Mbps data rate), and DIMM densities that can reach 288MBytes with stacked DDR SDRAMs. The 184-pin DIMM form factor is designed to fit in the same space as the current 168-pin SDRAM DIMM used for PC-100 systems.

"Samsung is committed to offering DDR in our roadmaps because our customers are requesting a continuing evolution of traditional DRAMs, and because it makes good economic sense from a DRAM manufacturing point of view. It's also an interface technology that we have successfully ported to other products, including graphics memory and cache SRAMs," said Mian Quddus, Strategic Marketing Manager at Samsung.

"We are fortunate to have the resources at Samsung to support both DDR and Direct Rambus as complementary DRAM architectures to help our customers succeed."

"Samsung again distinguishes itself by providing a cost-effective memory solution with DDR SDRAM, a tangible product, not just a promise," stated Sherry L. Garber, Senior Vice President, Semico Research Corp., Phoenix, Ariz.

The 64Mb-based DDR DIMMs will enter production in late Q3 in concert with the availability of sockets, clock drivers, and registers from other parties who support DDR SDRAMs. DDR SDRAM is forecasted to grow to more than a third of the total DRAM market demand in 2001 from a start in 1999.

Reference Data DDR interface technology has been applied to the traditional multiplexed SDRAM architecture. In the future, both multiplexed and packet-style DRAMs will continue to coexist to answer the diverging needs of PC, server, workstation, data communications, and consumer electronics markets.

Multiplexed DRAMs operate with wide data paths (typically 64-288 bits) and at lower frequencies to achieve maximum bandwidth. This provides flexibility, high system memory capacity and power efficiency in systems using significant amounts of memory. Bandwidth is derived through system design using lower cost DRAM technology. Initial designs for DDR SDRAM are in applications such as servers, workstations, and data communications systems, with entries in the PC and consumer market to follow.

Packet DRAMs operate with narrow data paths (typically 8-36 bits) and at higher frequencies to achieve maximum bandwidth. This provides high performance in systems using few DRAMs. Bandwidth is derived through the DRAM design using higher performance DRAM technology. For that reason, initial designs for packet DRAMs are in applications such as graphics cards, consumer electronics, and business desktop PCs.

Samsung supports DDR SDRAM as the continued evolution of multiplexed DRAMs, and Direct Rambus for the introduction of packet DRAMs. DDR interface technology allows Samsung to continue to reuse depreciated plants and equipment, critical in this time for any DRAM supplier. Samsung also decided to support Direct RDRAM over any other packet DRAM because it provides the best bandwidth-per-chip. Direct Rambus carries the endorsement of Intel for inclusion in 1999 desktop PCs. Samsung Semiconductor