Chips: Xicor Announces Industry's Smallest Footprint EEPROM Devices

Edge: Work-Group Computing Report, August 24, 1998

    The serial XBGA devices are sampling now and will be in

production by Q4/98.

Prices in 10,000 quantities for the 64 Kbit devices are:

X84641 (MPS Interface)                         $1.70

X25650 (SPI Interface)                         $1.80

X24640 (I2C Interface)                         $1.90

Prices in 10,000 quantities for the 128 Kbit devices are:

X84129 (MPS Interface)                          $2.75

X25138 (SPI Interface)                          $2.85

X24128 (I2C Interface)                          $2.95

Xicor, Inc. Monday announced the industry's first EEPROMs to use chip-scale packaging.

The die-sized Xicor Ball Grid Array (XBGA) package is less than half the size of today's smallest EEPROM packages.

The small footprint devices will give engineers extra board space to design in additional functions, and shrink the size and cost of their products. These products include cellular telephones, pagers, notebook PCs, PDAs, Global Positioning Systems, hearing aids, medical monitors, etc.

The XBGA EEPROMs are the ultimate in memory integrated circuit packaging because they have a die-sized footprint with the advantages of robust die protection.

Hard glass and epoxy together seal and protect the die, to deliver reliability performance comparable to standard plastic packages and enable placement and soldering with standard SMT (Surface Mount Technology) assembly equipment. XBGA manufacturing is done in the water fab and does not use bonding wires, resulting in competitive cost and die-sized package.

Xicor's family of XBGA EEPROMs is available with serial interfaces including I2C, SPI (Serial Peripheral Interface) and MPS (Micro Port Saver). The devices are ideal for battery-powered products and smart cards because of their tiny, low profile, lightweight package, and their low voltage operation (down to 1.8V) and low standby current (less than 1uA).

Smart Cards can benefit from the small size, thinness and mechanical strength of the XBGA.

According to Siamak Sani, director of product marketing, "This new XBGA technology brings the benefit of maximum packing density without requiring the development of new printed circuit board assembly technology by our customers. For example, the 128K XBGA EEPROM takes about a third of the board area currently occupied by the smallest 8-lead SOIC packages.

"The XBGA packages are durable and protect the die from the environment. They have demonstrated excellent thermal dissipation, solderability, temperature cycling and moisture resistance. Processing all dies concurrently while they are still together in wafer form makes the XBGA technology cost competitive.

"We intend to apply this technology across additional Xicor product lines to bring the benefits to additional applications and new markets," concluded Sani.

The first members of Xicor's XBGA family are three serial EEPROMs at 128 Kbit density and three at 64 Kbit density. These serial devices are available with one of three interfaces including I2C, SPI (Serial Peripheral Interface) and Xicor's high speed MPS (Micro Port Saver).

The MPS interface is a Xicor innovation that frees interface ports by connecting directly to the system bus of most popular microcontrollers, microprocessors and ASICs, while the I2C and SPI interfaces require dedicated ports.

Availability and Price

About New Packaging Technology The new XBGA technology is designed for conventional SMT printed circuit board assembly. Standard automated assembly equipment places the XBGA on the printed circuit board and a standard solder reflow process concurrently connects the XBGA device and the rest of the components to the conductive traces on the board.

The XBGA is essentially a tiny sandwich of glass containing a silicon integrated circuit die surrounded by epoxy. The products are built using a chip scale packaging technology developed by ShellCase Ltd., based in Israel. The XBGA manufacturing begins with a fully processed silicon wafer containing the EEPROM dies on its front side.

An aluminum layer is deposited, defined and etched, to form leads extending from the dies' input, output and control "pads" into the "streets" between the dies (these leads will be connected at a later step to solder bumps which will be the external terminations of the device).

In contrast, other chip scale package types and traditional plastic packages use thin wires to connect the dies' bonding pads to the package's outside terminals.

Using electronic-grade epoxy, a thin glass wafer is bonded to the frontside of the silicon wafer which contains the active devices. The silicon wafer is then thinned from the inactive backside down to less than 100um. Following that, the inactive silicon material between the dies is removed by etching, leaving all the separated dies and their leads still attached to the glass wafer.

Another layer of electronic grade epoxy is used to fill the gaps between the dies and to attach a second thin glass wafer to the back of all of the circuits. This creates the glass and epoxy "sandwich". The first glass layer that was attached to the frontside is then sawed through with a tapered blade to cut the internal metal leads described above and expose their edges.