Motorola Announces Intellectual Property Interface - IPI - Standard To Speed Development Of Embedded Applications; - Company Business and Marketing

Edge: Work-Group Computing Report, Dec 20, 1999

The IP Interface (IPI) standard, the first in a series of standards to be released through the SRS, was developed by Motorola's System-on-a-Chip Design Technology (SoCDT) organization, in close cooperation with experienced designers across Motorola and EDA vendors. The standard is available to the industry and can be downloaded free of charge through the Motorola website.

"Motorola's SRS is one of the most impressive sets of VC/SoC Standards we've ever seen in terms of overall vision, completeness, consistency, content and clarity," said Larry Rosenberg, Chair of VSIA's Technical Committee, and Larry Cooke, founding chair and on-going visionary for VSIA's On-Chip-Bus (OCB) Development Working Group (DWG), both acting as independent consultants in a visit to Motorola's SPS Austin site. "In some areas, such as Verification, Certification and catalog-search metadata, Motorola is well ahead of VSIA, and we're hoping they will be donated as a seed to us."

The IP Interface Standard covers the interblock communication needed in a SoC chip. Cooke noted, "It is one of the most comprehensive communication interface specifications I have seen. Virtually all the signals between IP/VCs in a SoC are covered by the specification."

The Standard provides interfaces for inter-processor, system, and peripheral buses, global signals, test and SoC I/O. The approach calls for the use of gaskets to connect IP/VCs with these interfaces to Motorola's internal On Chip Buses. The interface for the peripheral bus gasket is very similar to the OCB's peripheral Virtual Component (VC) Interface.

"It should be easy to create a gasket with a Peripheral VC Interface to integrate third party IP/VCs into their SoCs. We are encouraging Motorola to support the VC Interface and become more active in VSIA," said Cooke.

The IPI Standard allows modules to easily connect to other compliant modules and different CPU cores, accommodating bus widths from 8 to 64 bits. It designates the set of required and optional signals, along with associated protocols for different interface functions, such as interfaces to a peripheral bus or system test signals. The Standard includes specifications and bus bridges as design aids, and bus functional models and bus monitors for verification.

Four high level areas were studied in detail: Documentation, IP/VC Block Deliverables, RTL Coding Standards, and the IPI Standard. In addition, 8 other documents were reviewed, including Physical Standards, Analog/Mixed Signal, Design for Test, Functional Verification, and Libraries.

System-on-a-chip designs typically make use of a hierarchy of buses. The hierarchy is used to best match the capabilities of the bus with the requirements of the module that is connected to the bus. The system bus acts as the "backbone" by connecting the processor core to other system modules such as a DSP or DMA controller. The peripheral bus typically connects those modules that do not have efficient bus master access as a high priority design constraint.

The IPI Standard defines a set of common architecture, micro architecture and I/O signal standards for the design and verification of reusable system-on-a-chip modules. These modules are normally designed in a high-level description language (HDL) such as Verilog or VHDL.

The goal of this new Semiconductor Reuse Standard is to enable full reuse of the IP/VC block, without modification to the IP/VC block, and to significantly reduce the design cycle time. The specification covers the parts of an IP/VC block which are divided into different functional interfaces, defined by colored-line designations. This "color coding" approach divides the peripheral into the following seven interfaces:

- Green-Line which defines the set of global signals which are parts of a module and not included on any of the other colored-lines.

- Magenta-Line which defines the connections between the IP and the other System-on-a-Chip components in which it is being used.

- Sky Blue-Line which defines functional signals for accessing a peripheral's architecture registers.

- Dark Blue-Line which defines the connections between the IP that augments the early definitions of the peripheral interface to allow for modules that are capable of initiating DMA transactions.

- Indigo-Line which defines the connections between the IP that augments the early definitions of the peripheral interface to allow for modules that are capable of initiating interrupt requests.

- Purple-Line which defines the signals that cross the line between a peripheral's core logic and its interface to an I/O pad.

- Tan-Line Standard defines the signal connections at the boundary of the IP that are necessary to conduct testing of the IP.

This first implementation of the IPI standard is a solution for lower-performance slave-only peripherals, which are normally connected to a peripheral bus. This solution includes the signals needed to provide basic slave cycles for communication with the rest of the system, and a simple interface to the outside world through I/O pad connections.