Motorola Unveils Plans for First StarCore-Based Product. The MSC8101 is the industry's first DSP optimized for the "packetized" world, supporting ATM, Fast-Ethernet and fast TDM highways - Product Announcement

Edge: Work-Group Computing Report, Sept 20, 1999

A new digital signal processor (DSP) from Motorola featuring an on-chip network interface, is the first to use Motorola's new Star*Core DSP core technology.

This new product represents a dramatic leap in DSP technology, surpassing previously available devices in performance, networking capabilities, compiler efficiency, flexibility, and power efficiency. Developers of next-generation communication and networking infrastructure will soon be able to use this new Star*Core SC140-based DSP in all types of high-performance networking DSP applications.

The MSC8101, with a 300 MHz DSP core, offers four Arithmetic Logic Units (ALUs) providing 1200 DSP MIPS (3000 RISC MIPS), a high-performance 150 MHz Communications Processor Module (CPM) programmable network protocol engine, 512KB (256K 16-bit words) of on-chip Static RAM (SRAM), a 100 MHz 64- or 32-bit PowerPC bus interface, and a programmable memory controller.

On-chip peripherals such as a 300 MHz Enhanced Filter Coprocessor (EFCOP) and a powerful centralized DMA engine push performance even higher.

The MSC8101 is the first DSP manufactured using Motorola's new 0.13 micron copper interconnect process technology. It operates with a 1.5 V core and an independent 3.3 V I/O power supply, dissipating about 500mW of power for the entire device, all in a space-saving 17mm x 17mm plastic package.

The definition of the MSC8101 was driven by the next revolution in the communication world. As the transition from analog to digital systems is well on the way, the next revolution will take us from the circuit switched networks to packet switched networks. In addition to today's packetized data, tomorrow's system must handle packetized real-time streams such as speech and video.

DSPs, which have always been optimized for real-time applications, will be required to interface to packetized backbones such as 155 Mbps ATM backplanes.

Motorola's MSC8101, equipped with its unique programmable 32-bit RISC CPM, runs the networking protocol layers, thereby enabling the MSC8101 to link directly to packetized backbones, such as ATM and Fast Ethernet, as well as PCM highways such as E1/T1 and E3/T3.

This powerful CPM engine is based on the CPM from Motorola's popular PowerQUICC II (MPC8260) networking microcontrollers, used by all of the leading top-ten networking companies.

To minimize time-to-market, the MSC8101 utilizes the compiler-efficient SC140 core, the most compiler friendly DSP core in the industry, equipped with top-of-the-line software development tools. To minimize hardware development time, the MSC8101 is equipped with a well-proven, industry-standard, PowerPC (60x-compatible) bus.

At 100 MHz bus operating speed and 64- or 32-bit width (programmable), the PowerPC bus enables the MSC8101 to easily hook to PowerPC bus devices and shared memory sub-systems.

Additional system interface flexibility is provided through a separate enhanced 16-bit parallel Host Interface (HID16) that supports a variety of microcontroller, microprocessor, and DSP bus interfaces in conjunction with the PowerPC bus interface.

Infrastructure systems are driven by performance density. To minimize board space requirements, the MSC8101 integrates four megabits (512K bytes) of on-chip zero-wait-state memory, which holds the program and data required in many of the target applications.

This on-chip memory may eliminate or reduce accesses to off-chip memory, increasing system performance and lowering system power consumption and cost.

To maximize the number of channels each MSC8101 can process, the device integrates the Enhanced Filter Coprocessor (EFCOP), which boosts performance in filtering operations vital to such DSP tasks as echo cancellation. A sophisticated 16-channel DMA engine offloads the core from all data shuttling in the system.

To further reduce board space requirements, the MPC8101 comes in a 17mm x17mm plastic package.

The MSC8101 is the first product in the industry to offer this combination of DSP, PowerPC, and CPM technologies all in a single integrated device. It is Motorola's unique position in the industry to offer such capabilities for the communications and networking infrastructure market.

"The MSC8101 consists of an extremely powerful DSP engine that has been married with Motorola's market-leading communications processor architecture and its widely-supported PowerPC bus," said DSP market watcher Will Strauss, president of Forward Concepts (Tempe, AZ).

He went on to say, "The MSC8101 opens the door for distributed systems where the DSP processes the data directly from the network stream."

"Our MSC8101 is the first chip to integrate the SC140 DSP core unveiled by the Star*Core alliance last April," said Daniel Artusi, vice president and general manager of Motorola's Networking and Computing Systems Group.

"This is a genuine breakthrough for performance-intensive applications in wireless and wireline infrastructure equipment such as Internet telephony gateways, next-generation digital cellular infrastructure systems, xDSL telephone equipment, and multi-channel modem banks.