IBM Adopts Cadence Chip Assembly Router for Next-Generation Microprocessor Designs - Company Business and Marketing

Edge: Work-Group Computing Report, Jan 10, 2000

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, has revealed the role its Cadence chip assembly router played in the design of two of the world's fastest microprocessors from IBM.

The Cadence chip assembly router is a constraint-driven, shape-based, place and route solution for custom and structured custom integrated circuits (IC). It provides correct-by-construction implementation of strict timing, noise control, and topology requirements for deep-submicron (DSM) designs.

Developed by a team led by Cadence Fellow, David Chyan, the most recent recipient of the Gene Marsh Award for Technical Innovation (http://www.cadence.com/press_box/na/pr/1999/10_27b_99.html), the chip assembly router accounts for resistance and capacitance (R/C) effects occurring at 0.18 micron and below that induce crosstalk, clock skew, and other phenomena as wire widths and the distances between wires shrink.

"We selected the Cadence chip assembly router because it supported the required wiring density within the hierarchies, enabled users to write their own rich set of rules to customize the router, had an easy-to-use interactive wire editor, and easily integrated within the IBM custom design methodology flow," said Dale Hoffman, IBM manager, Advanced Processor Subsystem Group.

"Our design team was very satisfied with the ease of use of the Cadence chip assembly router and the performance it achieved."

Further details on IBM's use of the chip assembly router are available online at http://www.cadence.com/technology/chip/success/.> Breakthrough Performance, Breakthrough Tools

IBM was more than doubling performance with the recent introduction of its G5 and G6 complex instruction set computer (CISC) microprocessors, some of the world's fastest commercial parts. Used in IBM's world-standard mainframe and server products, the G5 and G6 are highly sophisticated semiconductor designs and, notably, both achieved first-silicon success in manufacturing.

The IBM design team faced a particularly difficult task with the G6, according to Jim Hogan, Cadence fellow, "The 25-million-transistor, 635MHz G6 was migrating from aluminum to copper wiring, part of a widely publicized effort by IBM to tackle interconnect and crosstalk issues. We are very excited that IBM chose the Cadence chip assembly router to tackle advance design."

Even though copper presented a new set of implementation and verification challenges, the Cadence chip assembly router was more than equal to the task. "The design issues we faced due to the introduction of the copper process were easily handled by the Cadence router along with our blockage modeling methodology," Hoffman said.

"Working with Cadence," Hogan noted, "IBM created a design flow that incorporated the chip assembly router in record time. This new flow enhanced the group's already formidable microprocessor-design skills, and added capabilities stemming directly from the Cadence router." A partial list of the expanded microprocessor design capabilities include:

* Unit/chip wiring contract generation, controlling wiring resource sharing between different levels of the hierarchy

* Multiple width and clearance support, simplifying interconnect rule management and aiding timing closure

* Rapid net crosstalk and ground-rule violation repair using correct-by-construction features

* Rich, flexible format for inputting crosstalk rules before or after routing helped to avoid or correct errors at every conceivable stage of the design

"The use of the interactive wiring editor allowed the rapid fixing of nets violating the crosstalk limits and nets with wiring technology ground rule violations," said Allan Dansky, IBM senior engineer, Advanced Processor Group. "These changes were always correct because of the tool's correct by construction methodology."

Additional information on IBM's microprocessor design, the Cadence chip assembly router, and complementary Cadence electronic design automation (EDA) tools and implementation services are available at http://www.cadence.com/technology/chip/, by e-mail at cps_group@cadence.com, or by dialing 800/746-6223.

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products.

With more than 4,000 employees and 1998 annual sales of $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN.

More information about the company, its products, and services may be obtained from the World Wide Web at www.cadence.com.