Magma's New Blast Chip System Delivers Fast RTL to Silicon Design Flow for Multi-Million Gate Designs - Product Announcement

Edge: Work-Group Computing Report, June 12, 2000

Realizing its vision to meld logical and physical design, Magma (Magma) Design Automation Inc. will demonstrate this week a single Electronic Design Automation (EDA) software system that takes an integrated circuit (IC) from register-transfer level (RTL) through final implementation. Its Blast Chip IC Implementation System integrates the newly released gain-based synthesis technology with Blast Fusion, the physical design system introduced last year.

Blast Fusion performs full chip design and features a multi-million gate-count capacity . The system performs synthesis, logic optimization, clock, power and timing estimation, extraction and place and route, as well as signal integrity and congestion management. It is designed to take full chips and large designs from RTL through GDSII, allowing partitioning to be based on design or project management requirements rather than on tool capacity limitations.

With Blast Chip, Magma extends its unified data model architecture and built-in tools to include synthesis. Using a single data model throughout the design flow, Blast Chip can optimize Magma Introduces Blast Chip RTL to GDSII Chip Implementation System page 4 an entire design for the best timing and signal integrity results without any iterations. As a result, it significantly reduces both the logical and physical design cycles.

The Blast Chip IC Implementation System will be demonstrated at the Design Automation Conference (DAC) today through Wednesday, June 7, at the Los Angeles Convention Center.

EXTENDING FIXEDTIMING, A UNIFIED DATA MODEL, AND SIGNAL INTEGRITY THROUGHOUT RTL TO GDSII FLOW

Like the Blast Fusion physical design system, Blast Chip is based on the Magma FixedTiming methodology and unified data model architecture. The FixedTiming methodology delivers the best timing without iterations between logical and physical design. This methodology enables Blast Chip and Blast Fusion to accurately determine the best timing prior to detailed layout, and to maintain that timing throughout the design flow.

Unlike common databases used by conventional point-tool systems, Magma's unified data model architecture allows an integrated suite of logical and physical design and optimization engines and analysis tools to operate concurrently on an entire design. Also unique to the Magma system's architecture are built-in signal integrity tools that automatically detect, prevent and correct signal integrity problems such as crosstalk and antenna rule violations throughout the design flow. This capability eliminates the time-consuming, analysis and manual fixes that are traditionally performed post-layout.

The Blast Chip design flow (Synthesis, Physical Optimization, Physical Design) includes two important checkpoints that enable designers to maximize the performance of their chips. The RTL checkpoint is the first and occurs just after timing optimization. If timing here is not fast enough, RTL modifications or changes to timing goals must be made to improve the timing--no optimization techniques through Magma's or third-party synthesis tools will improve timing. The timing sign-off checkpoint occurs before detailed physical design and accurately reflects final timing of the design in layout. Blast Chip will deliver a layout that meets or beats the timing reported at this stage.

GAIN-BASED SYNTHESIS - A FAST, EFFICIENT APPROACH TO LOGIC DESIGN

Physical synthesis technology uses inaccurate wireload models and some initial placement data to estimate interconnect parasitics or delay. Based on these estimates, physical synthesis tools must evaluate thousands of combinations of cell sizes for each circuit topology within the chip in an effort to optimize timing. In order to perform these numerous evaluations, a typical synthesis tool can only handle about 100 to 200K gates at a time. Further, because cell size and the implementation of the chip is fixed before any meaningful physical design is performed, traditional tools deliver sub-optimal timing results.

Blast Chip performs synthesis through a combination of the FixedTiming methodology and a gain-based approach. Gain is the ratio of the output capacitance to the input capacitance of a gate and is a measure of the gate's drive capability. By establishing and maintaining a certain size/load ratio, timing can be determined prior to layout and held constant throughout the flow. During synthesis, Blast Chip does not have to evaluate numerous combinations of cell sizes for each circuit topology since the cell sizing is not determined until after synthesis. With this approach Blast Chip can synthesize millions of gates at once and determine optimal cell sizing based on the timing requirements and the actual loading present in the physical layout.

BETA-USERS OF BLAST CHIP

With a small, dedicated team, Magma developed Blast Chip in tandem with Blast Fusion. iCompression and MIPS Technologies began working with the system earlier this year and expect to complete their designs soon.