Hybrids lead the way to savings

Electronics Times, June 28, 1999

Microcontroller users are usually concerned with cost in their system designs which in turn means they are concerned with the elegance of their design solutions. Any tip or wrinkle which can take a few pence out of the end cost is worth trying in the effort to do enough with less.

Unfortunately, the common microcontroller-based system architecture is full of inelegancies which, if designers only had the opportunity, could be smoothed away to create a better and cheaper solution.

Take the standard microcontroller: its drawback is that it is exactly that, a standard component with little if any room for customisation. Though multiple package variants of a microcontroller may exist, designers are stuck with the instruction set and functions of the chip as is.

The memory interfaces are fixed too, set up for driving signals off chip through package leads and board traces to memory chips of a limited range of organisations. Though the reliance on standards, from signal protocols to package technology, does save cost, it does not offer an optimal solution to the system design problem.

The same is true with the memory aspects of the microcontroller system design they are standards-based rather than application-based. So designers may find themselves using a memory chip just under twice the size they need because that is the next standard increment in device size.

And, as with the microcontroller in the system, the memory will be organised, interfaced and packaged in a way that suits the majority of applications reasonably well rather than to best fit a specific application.

The obvious solution to the problem is to break away from standards and integrate microcontrollers and memory on a single chip. But this is fraught with problems beyond those of cost and design complexity: it is hard to build memory arrays efficiently in manufacturing processes optimised for logic performance; conversely, it is hard to build fast dense logic in memory processes.

In particular it is difficult to merge high-performance logic processes with the densest form of memory cell DRAM.

So why bother? Because DRAM gives the greatest memory density. According to Richard Foss, chairman of memory development consultants Mosaid Technologies, even a conservative DRAM cell design targeted for a logic process is an order of magnitude more dense than simple synthesised SRAM, and half an order of magnitude more dense than embedded SRAM arrays. That order of magnitude difference could be significant in systems terms.

For example, what would the cost advantage be of being able to embed enough memory on the microcontroller that an entire structure of on- chip cache and off-chip secondary cache could be done away with? It is this sort of system payback which is driving the creation of embedded memory/microcontroller hybrids.

One area where this merging of logic and memory functions can be particularly powerful is in graphics subsystems, in which the achievable performance is controlled by the rate at which individual bits of memory can be accessed and manipulated.

But as graphics performance has increased, so have the problems caused by getting data in and out of the framestore.

One novel approach to fixing this problem has been developed by Mosaid working with Accelerix, a multimedia chip design company based in Ottawa, and Symbionics, of Cambridge.

Together they have designed a chip which closely couples graphics processing elements with the memory array so that the effective bus width between the frame buffer and the processor which has to manipulate it is 4096 bits difficult if not impossible to achieve by linking standard chips across a PCB.

Although this design meant a complex restructuring of the DRAM arrays to match the embedded processor strategy of the graphics chip, Accelerix points out that even simple changes in existing DRAM arrays can yield powerful consequences.

For example, Accelerix says that, in standard DRAM, two-word lines in the same array are never simultaneously active. By sequencing them in one active row cycle, page to page copies are made and block writes are simplified. By adding further registers and logic elements into the array, more sophisticated processing can be done in the memory array itself.

Although such sophisticated integration of memory and processing is not open to all, embedded memory technologies are now becoming more widely available.

Mosys, a fabless memory company and technology licensor, has developed what it calls 1T SRAM. Whereas most static memories are built around a combination of six transistors, Mosys' patented technique creates a static memory around a modified single transistor structure.

By writing design tools which create memory arrays of the 1T cells and proving the approach in standard chips and on foundry manufacturing processes, Mosys is now making a powerful embedded memory technique more widely available.

The value of the technology looks set to be shown in a recent alliance between Mosys and Lexra, the R3000 processor clone company.