Trends in IP and design reuse

Electronics Times, March 15, 1999

Chris Edwards previews the ET-sponsored conference and exhibition

Now into its third year, the system-on-chip (SoC) conference IP99 reflects a rapidly maturing industry.

No longer is it about when designers will use intellectual property (IP) or routinely adopt design reuse practices, or even why, but how they will make it work. This year's programme has been designed to show how IP suppliers can make the most of their technology and for users to adopt the best practices in the industry.

Jointly sponsored by Electronics Times and US title EETimes, IP99 marks the first year in which the conference includes a half-day IP Business Forum.

Held on Monday 22 March, it kicks off in the afternoon with a series of presentations from ARM, Rapid, Simutech and the Virtual Socket Interface Alliance (VSIA) on the business model challenges that face companies working in the IP arena.

A panel discussion follows in which Richard Wallace, editorial director of EETimes, and Erach Desai, industry analyst for Credit Suisse First Boston, lead a team of panellists to examine what can be done to add value to the existing model for IP, design reuse and system-on-chip design.

Panellists from Cadence, ARM, TSMC, UMC and LSI Logic will line up for the evening dinner panel chaired by Rob Chaplinksy, general partner for Mohr Davidow Ventures. Following on from last year's dinner panel, Chaplinsky, with help from the audience, will quiz the panelists to find out just which are the right strategies for success in the IP industry.

Day 2 sees the conference turn to issues for SoC designers themselves. Opened with keynotes from Aart de Geus and John Bourgoin, CEOs of Synopsys and MIPS Technologies respectively, the day's sessions will concentrate on the issues that surround design reuse, both commercial and technical.

In the morning, the design for reuse and test and functional verification tracks examine the problems and solutions involved in creating reusable IP and how those blocks can be checked when inserted into a SoC design.

At lunchtime, Erach Desai will lead a panel with contributions from IP Valuation, Mentor Graphics, Synopsys and STMicroelectronics. Looking at the various aspects of IP construction and use, the panel poses the question: "What is the real value of IP?"

With a proliferation of business models and ways to buy IP, it examines whether the balance of power lies in the hands of the IP developers or the IP integrators building SoC designs.

Into the afternoon, the tracks split into one focusing on commercial and business issues and one focusing on implementation.

In the IP business track, the commercial aspects of reuse have taken on as much importance as technical considerations. With legal problems taking up more time than some design projects, the commercial stream will show how the IP business is evolving to handle them.

The implementation stream will take attendees through the creation of four types of IP block - from a general-purpose approach through to a gigabit Ethernet controller.

The day's sessions then move to a panel discussion on the challenges of incorporating IP into one million gate FPGAs. Representatives from FPGA design service provider Memec Design, IP vendor Lexra and Synplicity will join Altera and Xilinx to walk through the design flow and discuss various methods for implementing IP on large FPGAs.

The third day opens with keynotes from Bob Terwilliger, CEO of ARC Cores, and Jim Ballingall, vice-president of worldwide marketing for UMC Group.

The morning streams comprise one on reuse and verification, looking at the problems involved with IP written in different HDLs and protected models. The second stream, on co-design, looks at this technique for reducing time to market and its impact on design.

The lunchtime panel takes into account the short shelf life of much electronic technology. Licensed and internally developed IP has a shelf life of about 18 months. After that, the technology is displaced and begins to lose value.

Companies maintaining IP portfolios need to make sure that they not only have access to the technology which their customers currently demand, but also that they have access to the technology which their customers will demand in the future. So, the panel asks, how quickly do companies need to move in the IP market?

Moderated by Larry Rosenberg of VSIA, representatives from Dain Rauscher Wessels, GartnerGroup Dataquest, MoSys, Palmchip, Quicklogic and VLSI Technology will describe how they see the problems of keeping up with a fast-moving business.

The afternoon concentrates on integration and the relatively new area of configurable IP, blocks that can be customised for individual designs through front-ends or scripts.

Alongside that runs a tutorial session on a methodology for evaluating quality in IP and selection criteria based on the More system developed at Synopsys.

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