Processors at a price

Electronics Times, July 24, 2000

How to embed processors into the latest FPGAs is challenging strategists, says Nick Flaherty

Are you hard or soft? While that may seem a rather personal question, it is one that has had strategists at the two largest FPGA companies wracking their brains. All this is over processors and how to embed them into the latest field programmable devices.

The stakes are huge. The move aims to address a market of $50bn by 2003, including applications-specific standard products, and standard cell chips with embedded processors. By contrast, the traditional FPGA business would only be worth $5bn by that time, says Paul Hollingworth, European director of marketing at Altera.

Altera has taken a somewhat split approach, with simultaneous deals last month to embed ARM and mips 32bit processors as hard macros into base silicon of its devices. At the same time, it has been developing a 16bit processor architecture called Nios for use as a soft core for applications that need up to 50mips.

Xilinx, on the other hand, has gone the entirely soft route, taking the ARC configurable 32bit core to be embedded into the latest Virtex II parts.

One question that springs to mind is why this has not been done before? One reason is density, and that is also an issue for the hard or soft core approach. Only now are FPGAs reaching the densities where an embedded processor makes sense. It is all very well being able to use a processor core in an FPGA, but if that is all you can do, then both companies agree there is little point.

Now that the Apex family from Altera is reaching 1.5 million system gates (the first part shipped a matter of weeks ago), and Xilinx's Virtex II family is at one million gates today with two million promised later this year, and the prospect of 10 million next year, there is enough logic spare on these chips to add other system functions.

That is not so much an issue with the hard core approach of Altera. But with the Nios and ARC approaches, there has to be sufficient logic left over to make it worthwhile using an FPGA.

The ARC core occupies from 10,000 to 25,000 gates, which will take up 8 to 20% of a Xilinx Virtex FPGA, says Bippin Parmar, strategic marketing director of ARC.

"We are convinced that soft IP is the way to go," he said. "The reality of embedded software development is the problems happen when the chip comes back from the foundry and you have to rewrite code to compensate for a shortfall in the asic performance."

This becomes even more compelling when it becomes practical in Xilinx's low-cost Spartan II family of devices, which will happen probably with the move to the Virtex III family next year. If density is really an issue, there are also different configurations of the multipliers in the core for either higher speed or lower gate count, varying between 2000 and 5000 gates, he says.

Soft cores have traditionally been viewed as lower performance than the optimised hard cores, and that is still true. But two things have changed.

One is that FPGA architectures are now far more geared to the control logic requirements of processors with embedded memory and multiplier blocks in the infrastructure of the devices. The second is the configurability of the processor. Xilinx is focusing on the system performance rather than the all-out megahertz or mips of the processor core.

CORES AND NETWORKS

Xilinx is taking on the ARC core in two forms: as a set of preconfigured cores in the standard library of intellectual property and also through a network of ARC-approved designed centres.

Bob Terwilliger, CEO of ARC, said: "There are some people that can take on the whole solution of a reconfigurable instruction set but there are some people that might be a little frightened to use it.

"We started working with programmable logic three years ago, and that's always exciting to ARC because programmable logic was the best way of doing a reconfigurable processor, supported by a complete tool chain, and the ability to do profiling and debugging with a single toolset."

Instruction use profiling is key to the approach as it allows designers to target the performance-critical areas of the design and either create a new instruction or a block of hard logic to handle it. That gives tremendous system performance advantages, says Terwilliger.

"What was really beneficial was when customers had a critical loop and can go off and write a small amount of assembly code and a couple of hundred gates of logic," he said. "That's where the customer has always seen the benefit of using the ARC as a configurable processor."

There are also advantages to having direct access to the processor core, says Terwilliger. Opening up direct access to the registers in the core and to intelligent peripherals means that the internal bus does not have to run faster to get all the data in and out of the core.

One example comes from an existing ARC design house, White Eagle in San Jose, California, that is already using Xilinx FPGAs to build a voice coder for GSM basestations. This needed a 1MHz clock with the ARC core in a Xilinx Virtex FPGA rather than 115MHz on a fixed instruction set processor.