MIPS core for 3D games at 600MHz

Electronics Times, June 12, 2000

MIPS Technologies has developed a high-speed microprocessor core intended for games machines and other embedded systems that need 3D graphics. It combines the company's 3D extensions disclosed last year with a dual-pipeline processor and a new on-chip bus.

The first implementation of the architecture will be a standalone processor to be made by NEC and Toshiba by the end of this year. That will be followed in mid-2001 by a hard-core IP tuned for system-on-chip designs.

In 0.18 micro m technology, this version is expected to run at up to 600MHz. A shrink to 0.15 micro m should push clock speeds to 750MHz.

The 20K processor and the 20Kc IP core both use a dual-issue MIPS64 integer core, joined to a 64Kbit-wide floating point unit. Largely aimed at 3D graphics geometry processing, the floating point unit can be split in half to run two 32bit operations in parallel. Most 3D geometry code needs an accuracy of no more than 32bit.

Because the design is intended for systems that cannot afford a fan, the designers have had to balance processing performance against power consumption.

The design is separated into a number of domains that can be powered separately. At 300MHz, the company reckons that the processor should consume about 900mW.

Mark Pittman, director of product marketing for MIPS, said: "We have a lot of clock conditioning circuitry. A clocked-down 20Kc could fit into handheld devices, running at 250 to 300MHz, say."

The low-power design extends to the way in which the various caches are implemented. As with other low-power risc processors, the data caches are split into sets that can be powered one at a time.

The processor attempts to predict which set will hold the data it is looking for. If that misses, the processor will search the other three sets in turn before going to main memory.

This approach lowers average power consumption at the cost of increasing latency if there is a miss in the cache. A similar approach is used in the translation lookaside buffer (TLB), which is used to convert the virtual addresses used by software into physical memory locations. The 20Kc has both a microTLB and a main TLB.

On each load or store, the four-entry microTLB is checked first and the main TLB is only powered up if the microTLB does not contain an entry that corresponds to the virtual address that it is given.

The content-associative memories used in most TLBs consume a large amount of power. As programs typically made repeated accesses to the same memory page before moving on to data in another, this approach helps save overall power.

To try to improve performance in branch-intensive code without moving to fully speculative execution - the 20K executes instructions in program order - the designers used a combination of branch prediction and lookahead techniques.

Instructions waiting to be executed are stored in two decoupled queues. On each cycle, four instructions are fetched from the cache, bringing a total of eight into the queue in total.

Logic in the instruction queue attempts to predict the outcome of up to two branches sitting in it. The unit can also predict the return address of subroutine calls, using a four-entry deep call stack.

For the 20K and 20Kc, the company has developed a follow-up to the SysAD bus used on its current processors. The MGBLink is intended for linking off-chip devices such as memories and uses series-terminated 1.5V HSTL logic signals running at 150MHz.

MGBLink is a split-translation bus that allows the results of reads to arrive in a different order to which they were issued. A credit-based scheme takes care of flow control across the bus to different peripherals.

The input and output buses are split. On the 20K family, MIPS has chosen to use a 64bit input and a 32bit output bus. This reflects the fact that write bandwidths are typically lower in 3D geometry processing than read bandwidths.

Both the input and output buses can be scaled to suit different application profiles and a 32bit input bus is possible.

"The input bus can be throttled back to 32bit but with a high- performance processor, you would run the risk of starving the processor," said Pittman.

For networking designs such as core switches and routers, the company is considering a stripped-down version of the 20Kc.

"A version without the 3D extensions is a possibility," said Pittman.