System-on-chip means `goodbye' to Harvard architecture

Electronics Times, June 12, 2000

The traditional Harvard architecture has had its day as more designs move to system-on-chip, according to Lucent Microelectronics.

It has developed a chip for the next generation of wireless basestations that integrates three StarCore SC140 DSP, developed with Motorola, and 6Mbits of global, unified memory.

The only way to integrate all this together is to use a split transaction bus, says Steve Dodsworth, manager of the wireless infrastructure applications group in Europe.

Lucent's research arm Bell Labs has developed a 128bit split transaction bus that runs at the 300MHz speed of the DSP cores. The resulting chip, the StarPro 2000, previously code-named Chameleon, produces 3600 MMAC/s or 9000mips, but it is the channel density that is more important, says Dodsworth.

The whole chip has been optimised for third-generation (3G) algorithms, with 16Kbyte data buffers on each core and 8Kbit program and data caches, handling up to 64 channels of voice or 64 channels of V.90 modem data.

The new architecture has been the only way to keep the power under 1.5W with a 1.5V core and 3.3V and 2.5V I/O.

The 0.16 micro m drawn process allows the chip to be packaged in a standard plastic ball grid array rather than a thermally enhanced package.

Dodsworth said: "Some of the pico basestation designs we are working on with customers are the size of an A4 pad and you can't have large heatsinks and large power supplies in them."

The split transaction bus approach will be even more key in the future as Lucent is looking to add customers' asics into the StarPro chip.

"Some of the 3G asics are around one million gates, and that is less than 10 square millimetres on the chip, but that's for the next process generation."