Philips' systematic approach

Electronics Times, March 6, 2000

Luke Collins previews a key conference on system-on-chip design issues

Philips Semiconductors will use this year's systems-on-chip conference, IP2000 in Santa Clara, to announce new methodologies for designing systems chips.

The company has just finished merging with VLSI Technology, which it took over last year, and now wants to bring the silicon intellectual property (IP) portfolios of the two together in a way which is easily accessible to asic designers.

Theo Claasen, chief technology officer of Philips and a keynote speaker at the conference, said: "Eight months in [to the merger] and the integration has been completed. If I had to make a judgement I think Philips had spent more time on a core reuse methodology, while VLSI was better at rapid prototyping and IP delivery."

Following the merger Philips has inserted its core reuse strategy, which it calls CoReuse, into VLSI's IP delivery tool, which is known as HDLI, for high-level design language integrator.

The company will also link what was the Philips platform strategy of basic system chip designs for a number of application domains, with VLSI's rapid silicon prototyping technique to produce what are effectively `silicon breadboards' for a number of marketplaces.

"We'll link rapid silicon prototyping to the platform concept based on applications domains, so we'll make a rapid silicon prototype around digital video, using a MIPS core, Trimedia [media processor] and video peripherals," said Claasen.

"In telecommunications terminals we have the ARM core, REAL, Oak, and Pine DSP cores and other peripherals," he added, "and the most important thing is that we'll guarantee that if you stick to the platform rules the software will run."

Claasen added that Philips is starting a platform development for digital audio applications, and is also working on a `car infotainment platform', including digital audio broadcast functions, navigation systems and communications. In the third-generation mobile telecoms market the company will focus on convergence products: "We need to increase the IP around telecoms platforms with functions borrowed from video, but tuned for low power."

Claasen's IP keynote will reflect the core theme of this year's conference - the systems in system-on-chip. To date, the IP conference series has focused on issues surrounding putting together blocks of silicon intellectual property, whether from third parties or from internal reuse libraries, to create a silicon chip. But this is clearly only half the story - a system is hardware and software and this year the conference has been adjusted to reflect this reality.

The first day of the conference looks once again at one of the critical infrastructure issues of system-on-chip methodologies - can they be made to work in a business sense? Highlights will include a keynote from Rob Chaplinsky of venture capital firm Mohr Davidow. And reflecting the move within large systems houses, a lunchtime panel will explore how centralised repositories of IP should be managed, and who takes responsibility for what. Other presentations, on simplifying the legal side of IP exchange, using FPGAs and on managing multi-site teams on large projects, will be capped off with a dinner panel discussion on the changing design culture necessary to make IP reuse work for system- on-chip designs.

CORE DEVELOPERS

As usual, the second and third days of this year's Santa Clara conference will focus on implementation issues. Claasen's Tuesday morning keynote, in which he will explain the upshot of Philips merger with VLSI Technology in terms of its impact on the merged company's SoC strategy, will be followed by the first of the conference's split-track sessions.

To show that SoC isn't all hype, one track on Tuesday morning will look at case studies of real designs implemented using SOC methodologies. Frontier Design of Belgium will explain how it used C language in the development of a speech recognition asic and IP core. Zilog will discuss how it tried out a 16bit risc/DSP core as an FPGA, and discuss how good a prototyping method it turned out to be for a design ultimately targeted to custom silicon. Finally Excel Consultants of the UK will explain how it took a design `from envelope to silicon' in two months.

In the concurrent track, three IP core developers will discuss their wares. PixelFusion, which has taped out a silicon implementation of its Fuzion150 3D graphics chip, will show how it will also offer this powerful processor as a scalable IP core. Infinite Technology will look at the pros and cons of various ways of linking IP cores. And Alcatel USA will discuss integrating a 104dB dynamic-range analogue front end with a 32bit risc processor on a single chip, and the tools, methodologies and IP they used to achieve that.

The lunchtime panel will discuss what it takes to create a reuse culture among engineers and in design teams. It will be followed in the afternoon by two further parallel presentation tracks. One track will run all afternoon, and focus on issues surrounding the integration of IP blocks. Summit will kick off with a discussion of a tool it has developed which can ease the creation of memory-mapped registers for intercommunication between IP blocks. Toshiba will follow will a discussion of its `Orbiter' platform, one of a number of emerging `silicon breadboard' concepts which are being offered to system chip designers as a quick way to try out hardware designs and system software before optimising the final chip design for cost.