Philips' systematic approach

Electronics Times, March 6, 2000

After coffee EnThink will discuss a number of synchronisation circuit offerings it has developed to make various types of IP block work together on a chip. Finally a researcher for the University of Turku in Finland explores how self-timed circuit techniques apply to SoC based designs, both within and between IP blocks.

Alongside the earlier part of this all-afternoon session a two- presentation session will look at evaluating IP quality. The first paper, by Artisan Components, will question whether IP quality is entirely in the eye of the beholder, or whether industry-wide standards will soon bring an external measure of quality to bear. The second, from a student at the University of Minnesota, will look at using fuzzy logic techniques to drive the choice of IP blocks.

A subsequent session will look at how generator techniques can be applied to parameterised IP to create unique solutions. Philips will discuss its DSP Builder tool which helps automate the integration of DSP blocks. Altera will explain how its parameterised error correction IP for FPGAs can be customised for an application.

On Wednesday a keynote from Mike Muller, executive vice president of business development for ARM Holdings will be followed by another morning of split tracks. In the first track the conference will concentrate on C and high-level-language based design - a critical emerging issue as designers try to move to a higher level of abstraction which can also offer flexible targeting to soft or hardware solutions.

The first presentation, by LSI Logic and Microsoft, will look at how an embedded design simulated on the VCS simulator, was set up to run Windows CE applications and device drivers. The idea was to move to a level where chip designs could be tried out within real world applications, rather than with simulation data alone. Another attempt to bridge that hardware/software gap will be presented by a team from Cadence Design Systems. They will look at an overall co-design methodology the company has been developing. Finally in this session on high-level language design, Co-Design Automation will explore what impact on the specification of a system-level language the demands of IP reuse might have.

A concurrent session will look at issues to do with design methodology. The first presentation, from GDA Technologies, will discuss a complete SoC development environment, known as SOCCER. This includes a bus hierarchy and reusable IP blocks, configurable design macros, a framework for integration and verification, plus tools for implementation and prototyping.

The second paper, from Synchronicity, will look at some of the issues surrounding designs done using IP. If you're using IP, be it from a third party or from an internal repository, you have effectively added virtual team members to your design staff, in the form of those who did the original design. What infrastructure do you need to make that work? The last paper in the session before lunch looks at a technique developed by a company called Sonics to ease IP block integration by decoupling IP cores from each other and the chip's main bus through a clearly defined open interface specification.