Free tool finds power hotspots - Brief Article

Electronics Times, Oct 23, 2000

Researchers at Penn State University, US, have developed an estimation tool that can point out power hotspots in hardware and software before systems are built and aim to distribute it from their website.

Dr Vijaykrishnan Narayanan, assistant professor of computer science and engineering, said: "By the time the design of today's large and complex processors have been set in silicon, it may be too late or too expensive to go back and deal with excess power consumption problems.

"Software is becoming an important aspect of emerging embedded systems, and the study of the integrated impact of software and hardware optimisations needs to be supported with new tools."

The team aims to distribute the prototype Simplepower tool free of charge from the university's website.

Instead of trying to model the workings of a processor at the gate or transistor level - the approach taken by existing power estimation tools - Simplepower uses a generic processor design. The instruction set that the team based the architecture on is derived from the Simplescalar architecture developed at the University of Wisconsin- Madison.

The idea behind Simplepower is that architectural changes to the underlying architecture will carry through to other processors with roughly the same benefits in terms of power.

Instead of trying to build transistor-level statistics, Simplepower uses the number of transitions in a given operation to calculate the power consumption of a particular approach. In a CMOS process, transitions account for the bulk of a processor's power consumption.

The transition-oriented approach was proposed in 1996 by Dr Mary Jane Irwin, professor of computer science and engineering at Penn State's Microsystems Design Laboratory.

The technique builds an energy model for each functional unit in the processor into a table that can be used to calculate the power consumed by the unit in reaction to an input transition.

That input transition may be a complete instruction or the toggling of a data line. In this way, the model can account for techniques such as clock gating, in which unused functional units are left unclocked, without having to model the gating activity at the circuit level.

The problem with the input transition method is that the tables can grow to be very large if the number of possible input combinations is high. For this reason, the team has used a clustering technique to collapse similar input transitions and energy patterns together.

Dr Narayanan says the tool can produce results in a fraction of time that a circuit-level tool would take, but can produce results that are within 10 to 15% of the competing technique.

The added speed would make it possible to get accurate estimates of the effect of compiler optimisations on power by `running' each instruction. This can be important because compiler optimisation can have a subtle effect on energy consumption as they may increase the bus traffic but reduce datapath activity or vice versa.

In tests designed to show how the tool could be used, the team used Simplepower to evaluate the impact of a gated pipeline optimisation, a high-level data transformation and a power-conscious post-compilation optimisation.

The team found that the optimisations reduced power consumption by 18 to 36% in the datapath, 62% in the memory system and 12% in the instruction cache data bus.

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