Cadence Accelerates Time-to-Volume for Advanced ICs With Model-Based, Variation-Aware Design Technologies; Provides "WYDIWYG" Capability

Market Wire, September, 2007

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced a broad set of new design products and capabilities for faster production of digital system-on-chip (SoC) designs. These new capabilities are included in advanced Cadence® SoC and custom implementation solutions that provide "what you design is what you get" (WYDIWYG) modeling and optimization for critical manufacturing variations during the design phase. This results in a manufacturing-intelligent physical implementation and signoff capability that correlates to foundry signoff.

Cadence will exhibit its 45nm design flows to leading semiconductor designers and design managers starting today at the CDNLive! Silicon Valley user conference. Production delivery is scheduled for the 7.1 release of Cadence Encounter® digital IC platform in October.

"At aggressive geometries, traditional design flows no longer provide accurate predictability, forcing designers to either guardband their designs excessively, or risk manufacturability problems," said Mike McAweeney, vice president of DFM marketing at Cadence. "By modeling key manufacturing processes within the implementation flow and optimizing early, we're reducing overall design time and improving designers' confidence that the chip will work as intended. With this approach, Cadence is providing a 'what you design is what you get' capability which brings manufacturing predictability back to the designer."

Implementation: Correct-by-Design for Advanced Silicon Geometries

A standard IC design consideration has long been manufacturing variability, which can result in both catastrophic and parametric yield failures. Traditionally, these failures were avoided through conservative "physical design rules," which prevented the implementation flow from creating any structures deemed risky. However, at advanced technology nodes of 65nm and especially at 45nm and below, the necessary "rules" are so conservative as to significantly limit IC performance and unnecessarily increase die area -- and still may not avoid all problems.

With this announcement, Cadence establishes a new approach to advanced process node design which addresses this challenge by going beyond "rules" and directly modeling critical elements of the manufacturing process -- lithography, chemical mechanical polishing (CMP), and random variation -- and using the models to produce a DFM-correct design through a prevention, analysis and optimization sequence.

To prevent lithography violations in SoC applications, the Cadence NanoRoute® router adds new technology which avoids gross lithography errors during routing for an immediate 50-80 percent reduction in lithographic "hotspots." Cadence Encounter QRC Extraction has been enhanced to support the advanced process models for accurate statistical parasitics extraction. For custom applications, a new capability of the Cadence Virtuoso® custom design platform leverages "recommended" rules as a starting point for further analysis and optimization. Accurate lithography analysis is accomplished using the Cadence Litho Physical Analyzer, formerly known as InShape from Clear Shape Technologies and recently acquired by Cadence. Any remaining lithography hotspots are optimized using a combination of grid- and space-based methods, the latter of which enables extremely fine-grained optimization and interconnect refinement.

The end result of this approach is a design which does not require excessive lithography correction during the photomask phase manufacturing -- it is essentially correct already.

CMP and random variation are managed through similar approaches, using the new Cadence's CMP Predictor analysis, and optimized through intelligent metal-fill and currently multicorner timing optimization methods.

Manufacturing Signoff: Model-Based and Statistical Timing Analysis

Cadence supports a suite of final analysis technologies that ensure the design will perform correctly after manufacturing. Critical lithography and CMP elements are analyzed using Cadence Litho Physical Analyzer and CMP Predictor. For timing analysis, a new statistical timing analysis system featured in the Cadence Encounter Timing System GXL, is being announced.

Encounter Timing System GXL offers two significant advantages over conventional multicorner timing analysis used in most 65nm design flows. First, Encounter Timing System GXL avoids the pessimism associated with "corners," many of which represent cases which are theoretically possible but increasingly unlikely -- a classic non-WYDIWYG symptom. And second, Encounter Timing System GXL executes in a fraction of the time usually required (or required by alternate competitive tools) to analyze timing on large sets of scenarios.

"Process variation is a major problem for our members doing sub-65nm designs, where today's corner-based design flows are too pessimistic leading to lower chip performance," said Nobuyuki Nishiguchi, vice president and general manager of Development Department 1 of Japan's Semiconductor Technology Academic Research Center (STARC). "We have been working with Cadence Encounter statistical timing analysis, optimization, and characterization for over a year and we are confident in its ability to deliver superb quality of results and yield improvement. Our exhaustive testing has proven that the Encounter statistical timing analysis is fast and accurate, and its seamless integration into the Encounter sign-off analysis and implementation environments makes it the most complete statistical timing technology available."