Advanced microprocessor test strategy and methodology

IBM Journal of Research and Development, Jul-Sep 1997 by Huott, W V, Koprowski, T J, Robbins, B J, Kusko, M P, Et al

This paper describes the overall test methodology used in implementing the S/390(R) microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test patterns and in measuring test effectiveness. Microprocessor advances in architectural complexity, circuit density, cycle time, and technology-related issues, coupled with IBM's high requirements for quality, reliability, and diagnosability, have made it necessary to develop testing methods and attain quality levels that far exceed what others have approached.

Introduction

The advent of deep-submicron technology has given rise to integrated circuits containing hundreds of thousands of logic gates, embedded memories approaching the megabit range, I/O counts in the thousands, and operating frequencies in the hundreds of MHz. Along with the benefits of such characteristics and the design flexibility necessary to achieve them come severe design and test challenges. In particular, traditional methods of testing semiconductor devices are quickly becoming obsolete. The use of functional patterns derived for design verification as manufacturing test patterns is becoming increasingly unacceptable. Some of the most severe problems associated with this approach are high test development times, defect coverages that are low or hard to measure, and poor diagnosability. As far back as fifteen to twenty years ago, test techniques were developed within IBM and in industry which based analysis on the design structure rather than on functionality [1]. Within IBM, these techniques have been evolving from the 308x testing in the early 1980s to the 3090* testing in the later '80s, to highdensity CMOS parts in the early '90s [2-13]. These techniques have led to the development of automatic testpattern generation (ATPG) algorithms and tools [14-19]. Although ATPG-based approaches to digital testing have met with some success, they also are becoming increasingly ineffective as chip sizes increase. Indeed, time requirements for ATPG algorithms grow nonlinearly in relation to the size of the circuit under test [20].

However, the largest problem with both the functional and ATPG-based test techniques is their reliance on the use of automatic test equipment to apply the test patterns to the device's external inputs and measure responses on the device's external outputs. This approach does not provide a means to adequately detect all of the device's internal defects. Direct access to the internal structures of a device is necessary. This requirement has led to the development of design-for-test (DFT) and built-in self-test (BIST) techniques and methods [21-27].

DFT techniques consist of design rules and constraints aimed at increasing the testability of a design through increased internal controllability and observability. The most popular form of DFT is scan design, which involves modifying all internal storage elements such that in test mode they form individual stages of a shift register for scanning test data stimuli and scanning out test responses.

Conceptually, the BIST approach is very simple. It is based on the realization that much of a circuit tester's electronics is semiconductor-based, just like the products it is testing, and that the challenge in ATE design, and many of the emerging limitations in ATE-based testing, lie in the interface to the DUT. In light of this fact, the BIST approach can be described as an attempt to move many of the already semiconductor-based test equipment functions into the products under test and eliminate the complex interfacing. This embedding of functionality has many benefits; some of the more important ones are the following:

The burden on and complexity of external test and dynamic stress equipment are drastically reduced.

The cost of product interface equipment, interface boards, space transformers, probes, etc. is reduced.

Embedded memories and other structures can easily be accessed for testing purposes.

All tests can be run at-speed, i.e., at the system operating frequency, which provides for better coverage of delay-related defects.

The approach can be used after product assembly for system and field testing.

The clear benefits of DFT and BIST encouraged the extensive use of these techniques in the design of the currently developed S/390* microprocessor and associated L2 cache chip. Indeed, the high complexity and density of these submicron CMOS-based devices, coupled with the need to optimize testing across all levels, minimize device silicon, optimize test equipment, decrease time to market, and achieve an extremely high shipped-product quality level, made the use of DFT and BIST essential. Novel and innovative BIST techniques were developed to address some of the unique test challenges that arose from these state-of-the-art designs.

This paper gives an overview of the test methodology and describes the various DFT and BIST techniques used. It then discusses some of the benefits of these DFT features in hardware debug. The paper concludes with a brief description of the test-generation software and faultmodel build, and the use of the fault-model/test software in generating the test data.