Metallization by plating for high-performance multichip modules

IBM Journal of Research and Development, Sep 1998 by Wong, K K H, Kaja, S, DeHaven, P W

Electrolytic plating is used to produce the interconnect wiring on the current generation of high-performance multichip modules used in IBM S/390(R) and AS/400(R) servers. This paper reviews the material and manufacturing requirements for successful implementation of a multilayer high-density wiring pattern involving electroplated copper metal and polyimide dielectric. Various strategies for the construction of thin-film structures (planarized and nonplanarized) are outlined, and the advantages of electrolytic plating over dry deposition techniques are described.

Introduction

Almost every electronic device is an aggregate of individual chips and discrete components. The ability to effectively package these components often plays a critical role in the ultimate performance of the device. This is especially true for high-end midrange and mainframe computers or servers, which, despite advances in chip design and ultralarge-scale system integration (ULSI) technology, can still consist of hundreds of individual chips.

Packaging in an electronic device serves four major functions. First, it provides the electrical connections (signal and power) among the components in the device. Second, the package provides mechanical protection to the chip die. Third, it acts as a space transformer (fan-out) between the dense chip connections and the less dense connections in subsequent mechanical assemblies. Finally, the package provides a means to dissipate the heat generated when the chips are powered. For high-end systems the first function, that of electrical connection, is critical to the ultimate performance of the computer. One widely adopted interconnection technique places multiple chips that require interconnections onto a common carrier, referred to as a multichip module (MCM). Depending on the nature of the carrier and the composition of the interlevel dielectric separating the electrical conductors in the package, an MCM can be categorized into one of three types: MCM-L, MCM-C, or MCM-D. For interconnection of the chips, MCM-L [1] uses printed-circuit-board wiring, while MCM-C uses cofired ceramic or glass-ceramic with thick-film metallization. MCM-D uses thin metal films and an organic dielectric over a rigid-base substrate such as silicon or aluminum nitride. This strategy is identical to that used in the fabrication of semiconductor interconnections, and permits MCM-D packages to achieve higher packing density and performance than the other two categories. Not surprisingly, it is also the most costly technology to implement. To reduce cost without a concomitant sacrifice in performance, a hybrid approach is taken by placing less critical wiring in a cofired ceramic base (MCM-C type) while concentrating the critical wiring in the MCM-D upper portion [2-4]. This approach is used in the IBM S/390* and AS/400* high-end servers.

A cross section of a typical MCM-D structure is shown in Figure 1. The base substrate is alumina ceramic with multiple levels of cofired molybdenum wiring. The critical wiring, which consists of five levels of copper lines with a polyimide dielectric, is deposited on top of this base. Metallized capture pads on the top surface of the ceramic connect the internal metallization in the ceramic with the first level of copper wiring (designated as MO). This is followed by a via level, VO, which connects MO to M1, the second wiring level. Alternating via and wiring levels are then sequentially fabricated, and finally end in a terminal metal layer, also known as the terminal surface metal, or TSM. The structure illustrated in Figure 1 contains five wiring levels (MO to M4) connected by four via levels (VO to V3). The narrowest wiring lines are of the order of 13 Am wide, 25 (mu)m apart, and approximately 5 (mu)m thick. Copper is chosen as the conductor line material primarily because of its high electrical conductivity. Polyimides are used as the interlevel dielectric material because they have relatively low dielectric constants and excellent thermal, mechanical, and chemical stability.

There are four common methods of copper film deposition. For features with less demanding ground rules (>25-(mu)m linewidth and 50-(mu)m spacing between lines), a sub-etch process is used [Figure 2(a)]. In this process, a blanket film of copper is deposited by sputtering or evaporation. The film is then photo-patterned with resist, followed by a wet etch to remove the unwanted copper. However, the inherent undercutting associated with wet etching makes this approach unsuitable for defining more aggressive features. Dry-etching techniques such as ion milling alleviate the undercutting, but these techniques are expensive, and minimizing back-sputtering of copper over other areas of the substrate is difficult.

An alternative procedure is metal stencil lift-off [Figure 2(b)]. Here the pattern is first defined by photoresist. Several metal layers (usually consisting of a diffusion barrier as well as the conductor) are then evaporated over the entire substrate. Because of the line-of-sight deposition during evaporation, there is very little sidewall coverage over the openings of the resist. After metal deposition, the resist is floated away, leaving a clean metal stack over the substrate. Lift-off was successfully used for the terminal metal layer of the IBM S/390 series of computers.