Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?

IBM Journal of Research and Development, Mar/May 2002 by Osburn, C M, Kim, I, Han, S K, De, I, Et al

The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure SiO^sub 2^ in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxide thickness (EOT)-for example, HfO^sub 2^, ZrO^sub 2^, and their silicates. Nevertheless, considerable challenges lie ahead if we are to achieve an EOT of less than 0.5 nm. If only a single molecular interface layer of oxide is needed to preserve high channel mobility, it seems likely that an EOT of 0.4-0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage (~10^sup 5^ A/cm^sup 2^). For junctions, the main challenge lies in providing low parasitic series resistance as depths are scaled in order to reduce short-channel effects. Because contacts are ultimately expected to dominate the parasitic resistance, low-barrier-height contacts and/or very heavily doped junctions will be required. While ion implantation and

annealing processes can certainly be extended to meet the junction-depth and series-- resistance requirements for additional generations, alternative low-temperature deposition processes that produce either metastably or extraordinarily activated, abruptly doped regions seem better suited to solve the contact resistance problem.

Introduction

Advances in silicon ULSI technology have historically been made by scaling of the device dimensions [1, 2]. According to scaling theory, both lateral dimensions (i.e., lithographic feature sizes) and vertical dimensions (e.g., junction depths) should be reduced to increase the packing density of devices while avoiding deleterious short-channel effects. The International Technology Roadmap for Semiconductors (ITRS) [3] provides a consensus scenario of how device parameters will scale for technology generations ranging from today's 130-nm technology to devices as small as 22 nm in the year 2016. The technology node parameter, also called the technology generation, represented the minimum lithographic image size in earlier generations of the Roadmap; now it refers to the DRAM half-pitch. This projected progress is even more remarkable when one notes that, for leading-edge microprocessor chips, the physical gate length is only 60% of the node parameter, and the effective channel length could be as little as half of the physical gate length. Thus, the Roadmap envisions devices having effective channel lengths well under 10 nm within the next 15 years. Furthermore, the recent historical rate of progress has been even faster than that predicted by the roadmaps or Moore's law. Each successive version of the ITRS Roadmap, from 1994 to 2001, has been more aggressive than the previous one: New technology nodes have been introduced more rapidly than expected, and, for each subsequent node, gate oxides have been thinner and junctions shallower than envisioned only a few years ago.

One explanation for the acceleration in progress is that it is a natural consequence of competition. Companies that wanted to attain a leadership status to stay competitive were forced to try to do better than the Roadmap. Because so many companies were successful, the industry as a whole moved faster than expected. One consequence of this rapid progress is that Roadmap projections became outdated almost immediately, forcing a need to update it every year. Figure 1 shows an example of the actual historical trend in gate-oxide thickness compared to Roadmap projections. Over the past ten years, gate dielectrics have scaled much faster than any of the Roadmap projections would have indicated. To compensate for the woefully conservative earlier estimates of technology parameters, later Roadmap committees have become more aggressive in projecting future scaling trends-to the point of straining current sensibilities.

Many individuals have noted the "sea of red" alongside the long-term technology requirements in the Roadmap, designating that there are no known solutions for almost any of the technology parameters. For example, the extrapolation of the historical trend in gate dielectric thickness extends below a molecular layer of SiO^sub 2^ in the year 2006! Thus, it is appropriate to seriously question both the basis of the requirements and whether or not we are trying to exceed the fundamental properties of materials and are doomed to failure.

This paper considers two of the key vertical scaling challenges, namely the gate stack (dielectric and electrode) and the extension junction. It first reviews and justifies some of the device requirements embedded in the Roadmap numbers for these elements. Then it presents a status report on work aimed at achieving materials and processes for end-of-the-Roadmap devices; finally, it provides a (speculative) prognosis on the likelihood of ultimately achieving Roadmap goals in a timely manner.