Embedded DRAM design and architecture for the IBM 0.11-(mu)m ASIC offering

IBM Journal of Research and Development, Nov 2002 by Barth, J E Jr, Dreibelbis, J H, Nelson, E A, Anand, D L, Et al

This paper presents an overview of the macro design, architecture, and built-in self-test (BIST) implementation as part of the IBM thirdgeneration embedded dynamic random-access memory (DRAM) for the IBM Blue Logic 0.11-um application-specific integrated circuit (ASIC) design system (CU-11). Issues associated with embedding DRAM in an ASIC design are identified and addressed, including fundamental DRAM core function, user interface, test, and diagnosis. Macro operation and organization are detailed and contrasted with traditional DRAM designs. The use of BIST, a key enabler for embedded DRAM, is discussed while highlighting innovations required by the embedded DRAM.

Introduction

As application-specific integrated circuit (ASIC) technologies expand into new markets, the need for denser embedded memory grows. To accommodate this increased demand, embedded DRAM macros have been offered in state-of-the-art ASIC library portfolios [1, 2].

This paper describes an embedded DRAM macro that extends the on-chip capacity to more than 40 MB, allowing historically off-chip memory to be integrated on chip and enabling System-on-a-Chip (SoC) designs. With memory on the chip, applications can take advantage of the high bandwidth naturally offered by a wide-I/O DRAM and achieve data rates greater than those previously limited by pin count and off-chip pin rates. Applications for this memory include network processors, digital signal processors, and cache chips for microprocessors. The integration of embedded DRAM into ASIC designs has intensified the focus on how best to architect, design, and test a high-performance, highdensity macro as complex as dynamic RAM in an ASIC logic environment. The ASIC environment itself presents many difficult elements that have historically challenged DRAMs-specifically wide voltage and temperature operating ranges and uncertainties in surrounding noise conditions. These challenges dictate a robust architecture that is noise-tolerant and can operate at high voltage for performance and at low voltage for reduced power. With the advent of embedded DRAM offerings in a logic-based ASIC technology [3], the performance of embedded DRAM macros has improved significantly over that of DRAM-based technologies. Users are increasingly replacing SRAM implementations with embedded DRAM, placing additional pressure on macro performance and random cycle time. This pressure extends into testing, where use of traditional direct memory access (DMA) is costly in silicon area and wiring complexity, and introduces uncertainty in performance-critical tests. A more attractive solution to this test problem is the use of a built-in self-test (BIST) system that is adapted to provide all of the necessary elements required for high fault coverage on DRAM, including the calculation

of a two-dimensional redundancy solution, pattern programming flexibility, at-speed testing, and test-mode application for margin testing [4, 51. This paper presents an overview of the macro design, architecture, and BIST implementation as part of the IBM third-generation embedded DRAM for the IBM Blue Logic 0.11-um ASIC design system (CU-11), offering a 4x density advantage over SRAM.

Fundamental DRAM operation

DRAM memory arrays are composed of wordlines (or rows) and bitlines (columns); see Figure 1. At the crosspoint of every row and column is a storage cell consisting of a transistor and capacitor [6]. The data state of the cell is stored as charge on the capacitor, with the transistor acting as a switch controlling access to the capacitor. With the switch on (wordline activated), charge can be read from or written to the storage cell. The rest of the DRAM support circuits are dedicated to controlling the wordlines and bitlines to read and write the memory array.

Overview of embedded DRAM

The CU-11 embedded DRAM macro has been developed around the idea of user simplicity while including a high degree of flexibility, function, and performance. For application flexibility, the embedded DRAM is growable in 1Mb increments to provide macro sizes from a IMb minimum to a 16Mb maximum and offers a 256-I/O width and a 292-I/O width for applications requiring parity. The wide I/O was chosen to provide maximum bandwidth; for applications that do not require the full width, bit-write control was included to facilitate masking. Multiple embedded DRAM macros can be instantiated on an ASIC die, enabling customers to make a performance/die-area tradeoff specific to their application. Figure 2 shows a high-level floorplan of the embedded DRAM. This architecture lends itself well to providing two modes of macro operation: single-bank and multi-bank interleave modes. The single-bank operation provides a simple SRAM replacement function, while the multi-bank mode extends the macro performance by allowing concurrent operations to independent banks.

Single-bank operation

Single-bank operation was intended to resemble an embedded SRAM, supporting simple broadside addressing with read/write control. To improve bandwidth, the user can optionally use page mode, which was carried over from conventional DRAM. The addressing is broken down as follows: